Firmware/MNRS-BM-BSP
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updates I2S registers adding fifo overflow status (#624)

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Eyck Jentzsch 2024-12-28 11:03:49 +01:00
parent deba022043
commit 9770c7b86c
1 changed files with 28 additions and 5 deletions
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33
include/ehrenberg/devices/gen/i2s.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-12-26 18:07:07 UTC
* Generated at 2024-12-28 11:01:24 UTC
* by peakrdl_mnrs version 1.2.9
*/
@ -72,12 +72,20 @@ typedef struct {
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_STATUS_LEFT_OVERFLOW_OFFS 4
#define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1
#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS)
#define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5
#define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1
#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
#define I2S_PDM_CLOCK_CTRL_MASK 0xff
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
#define I2S_PDM_FILTER_CTRL_OFFS 0
@ -158,6 +166,9 @@ inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
inline uint32_t get_i2s_status(volatile i2s_t* reg){
return reg->STATUS;
}
inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
reg->STATUS = value;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
@ -170,6 +181,18 @@ inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 4) & 0x1;
}
inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 5) & 0x1;
}
inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
}
//I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
@ -193,10 +216,10 @@ inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
}
//I2S_PDM_FILTER_CTRL