Use spn_checker in fpga_spn firmware
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@ -2,19 +2,11 @@
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#include "spn_regs.h"
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#include "spn_regs.h"
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#include "dma_regs.h"
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#include "dma_regs.h"
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#include "init.h"
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#include "init.h"
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#include <math.h>
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#include "spn_checker_regs.h"
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using spn = spn_regs<0x90000000>;
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using spn = spn_regs<0x90000000>;
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using dma = dma_regs<0xB0000000>;
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using dma = dma_regs<0xB0000000>;
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using spn_checker = spn_checker_regs<0x10040000>;
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// huge arrays of XSPN input and referance data
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extern std::array<uint8_t, 50000> input_data;
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extern std::array<double, 10000> ref_data;
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bool double_equals(double a, double b, double epsilon = 0.001)
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{
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return std::abs(a - b) < epsilon;
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}
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void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
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void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
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spn::mode_reg() = 0;
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spn::mode_reg() = 0;
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@ -37,24 +29,6 @@ void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) {
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dma::clear_interrupt_reg() = 1;
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dma::clear_interrupt_reg() = 1;
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}
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}
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void check_results(int addr, int k, int step) {
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int k0 = 0;
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bool result = 0;
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double *res_base = (double*) (addr);
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int * error_exit = (int *)0xF0000000;
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printf("Start result comparison %d - %d\n", k, k+step);
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for (int i = 0; i < step; i++) {
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if (!double_equals(res_base[i], ref_data.at(k0 + i))) {
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printf("XSPN ref %d comparison FAILED\n", k0 + i);
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result = 1;
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}
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}
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if (result == 1) *error_exit = 0x1;
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printf("Compared samples %d - %d with the reference\n", k, k+step);
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}
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/*! \brief main function
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/*! \brief main function
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*
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*
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*/
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*/
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@ -95,23 +69,30 @@ int main() {
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uint32_t out_beats = (step * result_bytes) / axi_bytes;
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uint32_t out_beats = (step * result_bytes) / axi_bytes;
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if (out_beats * axi_bytes < step * result_bytes) out_beats++;
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if (out_beats * axi_bytes < step * result_bytes) out_beats++;
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int in_addr = (int)input_data.data();
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int in_addr = 0x20010000; // place input samples in the SPI memory
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int out_addr = 0x800B0000;
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int out_addr = 0x20210000;
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int fpga_address_in = 0x10000000;
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int fpga_address_in = 0x10000000;
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int fpga_address_out = 0x20000000;
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int fpga_address_out = 0x20000000;
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// inject SPN input data
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spn_checker::input_addr_reg() = in_addr;
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spn_checker::num_input_samples_reg() = sample_bytes * step * iterations;
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spn_checker::start_data_trans_reg() = 1;
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spn_checker::output_addr_reg() = out_addr;
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//run_xspn(in_addr, out_addr);
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//run_xspn(in_addr, out_addr);
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for (int k = 0; k < iterations*step; k+=step) {
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for (int k = 0; k < iterations*step; k+=step) {
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printf("XSPN processes samples %d - %d\n", k, k+step);
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fpga_dma(1, fpga_address_in, in_addr, step * sample_bytes);
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fpga_dma(1, fpga_address_in, in_addr, step * sample_bytes);
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run_xspn(fpga_address_in, fpga_address_out, step, in_beats, out_beats);
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run_xspn(fpga_address_in, fpga_address_out, step, in_beats, out_beats);
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wait_for_interrupt();
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wait_for_interrupt();
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spn::interrupt_reg() = 1;
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printf("XSPN finished\n");
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printf("XSPN finished\n");
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spn::interrupt_reg() = 1;
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fpga_dma(0, fpga_address_out, out_addr, step * result_bytes);
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fpga_dma(0, fpga_address_out, out_addr, step * result_bytes);
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check_results(out_addr, k, step);
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spn_checker::offset_reg() = k;
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spn_checker::length_reg() = step;
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spn_checker::start_result_check_reg() = 1;
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//in_addr += step * sample_bytes; // 5 bytes in each sample
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in_addr += step * sample_bytes; // 5 bytes in each sample
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}
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}
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return 0;
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return 0;
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@ -0,0 +1,97 @@
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Thu Oct 01 15:45:55 CEST 2020
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// * spn_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#pragma once
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#include <util/bit_field.h>
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#include <cstdint>
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#define SPN_CNTL_REG_START_RESULT_CHECK 0x00
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#define SPN_CNTL_REG_OFFSET 0x10
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#define SPN_CNTL_REG_LENGTH 0x20
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#define SPN_CNTL_REG_OUTPUT_ADDR 0x30
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#define SPN_CNTL_REG_INPUT_ADDR 0x40
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#define SPN_CNTL_REG_NUM_INPUT_SAMPLES 0x50
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#define SPN_CNTL_REG_START_DATA_TRANS 0x60
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template<uint32_t BASE_ADDR>
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class spn_checker_regs {
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public:
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// storage declarations
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// BEGIN_BF_DECL(start_t, uint32_t);
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// BF_FIELD(start, 0, 1);
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// END_BF_DECL() r_start;
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uint32_t r_start_result_check;
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uint32_t r_offset;
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uint32_t r_length;
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uint32_t r_output_addr;
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uint32_t r_input_addr;
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uint32_t r_num_input_samples;
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uint32_t r_start_data_trans;
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static inline uint32_t& start_result_check_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_RESULT_CHECK);
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}
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static inline uint32_t & offset_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OFFSET);
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}
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static inline uint32_t & length_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_LENGTH);
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}
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static inline uint32_t & output_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_OUTPUT_ADDR);
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}
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static inline uint32_t & input_addr_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_INPUT_ADDR);
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}
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static inline uint32_t & num_input_samples_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_NUM_INPUT_SAMPLES);
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}
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static inline uint32_t& start_data_trans_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_CNTL_REG_START_DATA_TRANS);
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}
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};
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