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fix interrupt handler and Moonlight ROM size

This commit is contained in:
Stanislaw Kaushanski 2024-09-26 12:18:50 +02:00
parent ea5d61ec0b
commit 3484dc66e3
3 changed files with 75 additions and 60 deletions
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9
env/ehrenberg/init.c vendored
View File

@ -97,13 +97,14 @@ void __attribute__((weak)) interrupt_handler(unsigned) {
} }
uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){ uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { if ((mcause & MCAUSE_INT)) {
if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
handle_m_ext_interrupt(); handle_m_ext_interrupt();
// External Machine-Level interrupt from PLIC } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt(); handle_m_time_interrupt();
} else if(!(mcause&MCAUSE_INT)) { } else {
interrupt_handler(mcause& ~MCAUSE_INT); interrupt_handler(mcause& ~MCAUSE_INT);
}
} else { } else {
write(1, "trap\n", 5); write(1, "trap\n", 5);
_exit(1 + mcause); _exit(1 + mcause);

2
env/ehrenberg/rom.lds vendored
View File

@ -4,7 +4,7 @@ ENTRY( _start )
MEMORY MEMORY
{ {
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 1k rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
} }

118
env/entry.S vendored
View File

@ -10,66 +10,80 @@
.align 2 .align 2
.global trap_entry .global trap_entry
trap_entry: trap_entry:
addi sp, sp, -32*REGBYTES
sw x1, 1*REGBYTES(sp)
sw x2, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve #ifndef __riscv_abi_rve
addi sp, sp, -8*REGBYTES sw x16, 16*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp) // ra sw x17, 17*REGBYTES(sp)
STORE x5, 2*REGBYTES(sp) // t0 sw x18, 18*REGBYTES(sp)
STORE x10, 3*REGBYTES(sp) // a0 sw x19, 19*REGBYTES(sp)
STORE x11, 4*REGBYTES(sp) // a1 sw x20, 20*REGBYTES(sp)
STORE x12, 5*REGBYTES(sp) // a2 sw x21, 21*REGBYTES(sp)
STORE x13, 6*REGBYTES(sp) // a3 sw x22, 22*REGBYTES(sp)
STORE x15, 7*REGBYTES(sp) // t1 sw x23, 23*REGBYTES(sp)
#else sw x24, 24*REGBYTES(sp)
addi sp, sp, -16*REGBYTES sw x25, 25*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp) // ra sw x26, 26*REGBYTES(sp)
STORE x5, 2*REGBYTES(sp) // t0 sw x27, 27*REGBYTES(sp)
STORE x6, 3*REGBYTES(sp) // t1 sw x28, 28*REGBYTES(sp)
STORE x7, 4*REGBYTES(sp) // t2 sw x29, 29*REGBYTES(sp)
STORE x10, 5*REGBYTES(sp) // a0 sw x30, 30*REGBYTES(sp)
STORE x11, 6*REGBYTES(sp) // a1 sw x31, 31*REGBYTES(sp)
STORE x12, 7*REGBYTES(sp) // a2
STORE x13, 8*REGBYTES(sp) // a3
STORE x14, 9*REGBYTES(sp) // a4
STORE x15, 10*REGBYTES(sp) // a5
STORE x16, 11*REGBYTES(sp) // a6
STORE x17, 12*REGBYTES(sp) // a7
STORE x28, 13*REGBYTES(sp) // t3
STORE x29, 14*REGBYTES(sp) // t4
STORE x30, 15*REGBYTES(sp) // t5
STORE x31, 16*REGBYTES(sp) // t6
#endif #endif
csrr a0, mcause csrr a0, mcause
csrr a1, mepc csrr a1, mepc
mv a2, sp mv a2, sp
call handle_trap call handle_trap
csrw mepc, a0 csrw mepc, a0
lw x1, 1*REGBYTES(sp)
lw x2, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve #ifndef __riscv_abi_rve
addi sp, sp, -8*REGBYTES lw x16, 16*REGBYTES(sp)
LOAD x1, 1*REGBYTES(sp) // ra lw x17, 17*REGBYTES(sp)
LOAD x5, 2*REGBYTES(sp) // t0 lw x18, 18*REGBYTES(sp)
LOAD x10, 3*REGBYTES(sp) // a0 lw x19, 19*REGBYTES(sp)
LOAD x11, 4*REGBYTES(sp) // a1 lw x20, 20*REGBYTES(sp)
LOAD x12, 5*REGBYTES(sp) // a2 lw x21, 21*REGBYTES(sp)
LOAD x13, 6*REGBYTES(sp) // a3 lw x22, 22*REGBYTES(sp)
LOAD x15, 7*REGBYTES(sp) // t1 lw x23, 23*REGBYTES(sp)
#else lw x24, 24*REGBYTES(sp)
addi sp, sp, -16*REGBYTES lw x25, 25*REGBYTES(sp)
LOAD x1, 1*REGBYTES(sp) // ra lw x26, 26*REGBYTES(sp)
LOAD x5, 2*REGBYTES(sp) // t0 lw x27, 27*REGBYTES(sp)
LOAD x6, 3*REGBYTES(sp) // t1 lw x28, 28*REGBYTES(sp)
LOAD x7, 4*REGBYTES(sp) // t2 lw x29, 29*REGBYTES(sp)
LOAD x10, 5*REGBYTES(sp) // a0 lw x30, 30*REGBYTES(sp)
LOAD x11, 6*REGBYTES(sp) // a1 lw x31, 31*REGBYTES(sp)
LOAD x12, 7*REGBYTES(sp) // a2
LOAD x13, 8*REGBYTES(sp) // a3
LOAD x14, 9*REGBYTES(sp) // a4
LOAD x15, 10*REGBYTES(sp) // a5
LOAD x16, 11*REGBYTES(sp) // a6
LOAD x17, 12*REGBYTES(sp) // a7
LOAD x28, 13*REGBYTES(sp) // t3
LOAD x29, 14*REGBYTES(sp) // t4
LOAD x30, 15*REGBYTES(sp) // t5
LOAD x31, 16*REGBYTES(sp) // t6
#endif #endif
mret mret