diff --git a/env/ehrenberg/init.c b/env/ehrenberg/init.c
index 53c0848..8f6a88e 100644
--- a/env/ehrenberg/init.c
+++ b/env/ehrenberg/init.c
@@ -97,13 +97,14 @@ void __attribute__((weak)) interrupt_handler(unsigned) {
 }
 
 uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
-  if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
-    handle_m_ext_interrupt();
-    // External Machine-Level interrupt from PLIC
-  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
-    handle_m_time_interrupt();
-  } else if(!(mcause&MCAUSE_INT)) {
-    interrupt_handler(mcause& ~MCAUSE_INT);
+  if ((mcause & MCAUSE_INT)) {
+    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
+      handle_m_ext_interrupt();
+    } else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ 
+      handle_m_time_interrupt();
+    } else {
+      interrupt_handler(mcause& ~MCAUSE_INT);
+    }
   } else {
     write(1, "trap\n", 5);
     _exit(1 + mcause);
diff --git a/env/ehrenberg/rom.lds b/env/ehrenberg/rom.lds
index 24ac875..822d3fd 100644
--- a/env/ehrenberg/rom.lds
+++ b/env/ehrenberg/rom.lds
@@ -4,7 +4,7 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 1k
+  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
   ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
 }
 
diff --git a/env/entry.S b/env/entry.S
index fef8b9e..5091f8c 100644
--- a/env/entry.S
+++ b/env/entry.S
@@ -10,66 +10,80 @@
   .align 2
   .global trap_entry
 trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  sw  x1,  1*REGBYTES(sp)
+  sw  x2,  2*REGBYTES(sp)
+  sw  x3,  3*REGBYTES(sp)
+  sw  x4,  4*REGBYTES(sp)
+  sw  x5,  5*REGBYTES(sp)
+  sw  x6,  6*REGBYTES(sp)
+  sw  x7,  7*REGBYTES(sp)
+  sw  x8,  8*REGBYTES(sp)
+  sw  x9,  9*REGBYTES(sp)
+  sw x10, 10*REGBYTES(sp)
+  sw x11, 11*REGBYTES(sp)
+  sw x12, 12*REGBYTES(sp)
+  sw x13, 13*REGBYTES(sp)
+  sw x14, 14*REGBYTES(sp)
+  sw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  addi sp, sp, -8*REGBYTES
-  STORE x1, 1*REGBYTES(sp) // ra
-  STORE x5, 2*REGBYTES(sp) // t0
-  STORE x10, 3*REGBYTES(sp) // a0
-  STORE x11, 4*REGBYTES(sp) // a1
-  STORE x12, 5*REGBYTES(sp) // a2
-  STORE x13, 6*REGBYTES(sp) // a3
-  STORE x15, 7*REGBYTES(sp) // t1
-#else
-  addi sp, sp, -16*REGBYTES
-  STORE x1, 1*REGBYTES(sp) // ra
-  STORE x5, 2*REGBYTES(sp) // t0
-  STORE x6, 3*REGBYTES(sp) // t1
-  STORE x7, 4*REGBYTES(sp) // t2
-  STORE x10, 5*REGBYTES(sp) // a0
-  STORE x11, 6*REGBYTES(sp) // a1
-  STORE x12, 7*REGBYTES(sp) // a2
-  STORE x13, 8*REGBYTES(sp) // a3
-  STORE x14, 9*REGBYTES(sp) // a4
-  STORE x15, 10*REGBYTES(sp) // a5
-  STORE x16, 11*REGBYTES(sp) // a6
-  STORE x17, 12*REGBYTES(sp) // a7
-  STORE x28, 13*REGBYTES(sp) // t3
-  STORE x29, 14*REGBYTES(sp) // t4
-  STORE x30, 15*REGBYTES(sp) // t5
-  STORE x31, 16*REGBYTES(sp) // t6
+  sw x16, 16*REGBYTES(sp)
+  sw x17, 17*REGBYTES(sp)
+  sw x18, 18*REGBYTES(sp)
+  sw x19, 19*REGBYTES(sp)
+  sw x20, 20*REGBYTES(sp)
+  sw x21, 21*REGBYTES(sp)
+  sw x22, 22*REGBYTES(sp)
+  sw x23, 23*REGBYTES(sp)
+  sw x24, 24*REGBYTES(sp)
+  sw x25, 25*REGBYTES(sp)
+  sw x26, 26*REGBYTES(sp)
+  sw x27, 27*REGBYTES(sp)
+  sw x28, 28*REGBYTES(sp)
+  sw x29, 29*REGBYTES(sp)
+  sw x30, 30*REGBYTES(sp)
+  sw x31, 31*REGBYTES(sp)
 #endif
   csrr a0, mcause
   csrr a1, mepc
   mv a2, sp
   call handle_trap
   csrw mepc, a0
+
+
+  lw  x1,  1*REGBYTES(sp)
+  lw  x2,  2*REGBYTES(sp)
+  lw  x3,  3*REGBYTES(sp)
+  lw  x4,  4*REGBYTES(sp)
+  lw  x5,  5*REGBYTES(sp)
+  lw  x6,  6*REGBYTES(sp)
+  lw  x7,  7*REGBYTES(sp)
+  lw  x8,  8*REGBYTES(sp)
+  lw  x9,  9*REGBYTES(sp)
+  lw x10, 10*REGBYTES(sp)
+  lw x11, 11*REGBYTES(sp)
+  lw x12, 12*REGBYTES(sp)
+  lw x13, 13*REGBYTES(sp)
+  lw x14, 14*REGBYTES(sp)
+  lw x15, 15*REGBYTES(sp)
 #ifndef __riscv_abi_rve
-  addi sp, sp, -8*REGBYTES
-  LOAD x1, 1*REGBYTES(sp) // ra
-  LOAD x5, 2*REGBYTES(sp) // t0
-  LOAD x10, 3*REGBYTES(sp) // a0
-  LOAD x11, 4*REGBYTES(sp) // a1
-  LOAD x12, 5*REGBYTES(sp) // a2
-  LOAD x13, 6*REGBYTES(sp) // a3
-  LOAD x15, 7*REGBYTES(sp) // t1
-#else
-  addi sp, sp, -16*REGBYTES
-  LOAD x1, 1*REGBYTES(sp) // ra
-  LOAD x5, 2*REGBYTES(sp) // t0
-  LOAD x6, 3*REGBYTES(sp) // t1
-  LOAD x7, 4*REGBYTES(sp) // t2
-  LOAD x10, 5*REGBYTES(sp) // a0
-  LOAD x11, 6*REGBYTES(sp) // a1
-  LOAD x12, 7*REGBYTES(sp) // a2
-  LOAD x13, 8*REGBYTES(sp) // a3
-  LOAD x14, 9*REGBYTES(sp) // a4
-  LOAD x15, 10*REGBYTES(sp) // a5
-  LOAD x16, 11*REGBYTES(sp) // a6
-  LOAD x17, 12*REGBYTES(sp) // a7
-  LOAD x28, 13*REGBYTES(sp) // t3
-  LOAD x29, 14*REGBYTES(sp) // t4
-  LOAD x30, 15*REGBYTES(sp) // t5
-  LOAD x31, 16*REGBYTES(sp) // t6
+  lw x16, 16*REGBYTES(sp)
+  lw x17, 17*REGBYTES(sp)
+  lw x18, 18*REGBYTES(sp)
+  lw x19, 19*REGBYTES(sp)
+  lw x20, 20*REGBYTES(sp)
+  lw x21, 21*REGBYTES(sp)
+  lw x22, 22*REGBYTES(sp)
+  lw x23, 23*REGBYTES(sp)
+  lw x24, 24*REGBYTES(sp)
+  lw x25, 25*REGBYTES(sp)
+  lw x26, 26*REGBYTES(sp)
+  lw x27, 27*REGBYTES(sp)
+  lw x28, 28*REGBYTES(sp)
+  lw x29, 29*REGBYTES(sp)
+  lw x30, 30*REGBYTES(sp)
+  lw x31, 31*REGBYTES(sp)
 #endif
   mret