adds csr access functions

This commit is contained in:
2025-11-21 11:26:09 +01:00
parent 6e2607cecc
commit 328a961276
4 changed files with 17417 additions and 8 deletions

View File

@@ -21,6 +21,7 @@
#include "minres/devices/qspi.h"
#include "minres/devices/timer.h"
#include "minres/devices/uart.h"
#include <riscv/riscv_csr.h>
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
// values from memory_map.ld

View File

@@ -1,9 +1,8 @@
#ifndef _DEVICES_ACLINT_H
#define _DEVICES_ACLINT_H
#include <stdint.h>
#include "gen/aclint.h"
#include <stdint.h>
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) {
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
@@ -11,8 +10,18 @@ static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
}
static uint64_t get_aclint_mtime(volatile aclint_t* reg) {
uint64_t value = ((uint64_t)get_aclint_mtime_hi(reg) << 32) | (uint64_t)get_aclint_mtime_lo(reg);
return value;
// #if ( __riscv_xlen == 64)
// volatile uint64_t *mtime = (volatile uint64_t *)(RISCV_MTIME_ADDR);
// return *mtime;
// #else
uint32_t mtimeh_val;
uint32_t mtimel_val;
do {
mtimeh_val = get_aclint_mtime_hi(reg);
mtimel_val = get_aclint_mtime_lo(reg);
} while(mtimeh_val != get_aclint_mtime_hi(reg));
return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val);
// #endif
}
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) {

3790
include/riscv/riscv_csr.h Normal file

File diff suppressed because it is too large Load Diff

13609
include/riscv/riscv_csr.hpp Normal file

File diff suppressed because it is too large Load Diff