rework structure

hifive1-vp/riscv-bldc-forced-commutation/src/io/gpio.h

@@ -0,0 +1,89 @@
+/*
+ * gpio.h
+ *
+ *  Created on: 29.07.2018
+ *      Author: eyck
+ */
+
+#ifndef GPIO_H_
+#define GPIO_H_
+
+#include <sifive/devices/gpio.h>
+#include <cstdint>
+
+template<uint32_t BASE_ADDR>
+class gpio_regs {
+public:
+    static inline uint32_t& value_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_INPUT_VAL);
+    }
+
+    static inline uint32_t& input_en_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_INPUT_EN);
+    }
+
+    static inline uint32_t& output_en_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_EN);
+    }
+
+    static inline uint32_t& port_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_VAL);
+    }
+
+    static inline uint32_t& pue_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_PULLUP_EN);
+    }
+
+    static inline uint32_t& ds_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_DRIVE);
+    }
+
+    static inline uint32_t& rise_ie_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_RISE_IE);
+    }
+
+    static inline uint32_t& rise_ip_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_RISE_IP);
+    }
+
+    static inline uint32_t& fall_ie_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_FALL_IE);
+    }
+
+    static inline uint32_t& fall_ip_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_FALL_IP);
+    }
+
+    static inline uint32_t& high_ie_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_HIGH_IE);
+    }
+
+    static inline uint32_t& high_ip_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_HIGH_IP);
+    }
+
+    static inline uint32_t& low_ie_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_LOW_IE);
+    }
+
+    static inline uint32_t& low_ip_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_LOW_IP);
+    }
+
+    static inline uint32_t& iof_en_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_IOF_EN);
+    }
+
+    static inline uint32_t& iof_sel_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_IOF_SEL);
+    }
+
+    static inline uint32_t& out_xor_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+GPIO_OUTPUT_XOR);
+    }
+
+};
+
+
+
+#endif /* GPIO_H_ */

hifive1-vp/riscv-bldc-forced-commutation/src/io/pwm.h

@@ -0,0 +1,122 @@
+/*
+ * pwm.h
+ *
+ *  Created on: 29.07.2018
+ *      Author: eyck
+ */
+
+#ifndef PWM_H_
+#define PWM_H_
+
+#include <sifive/devices/pwm.h>
+#include "util/bit_field.h"
+#include <limits>
+#include <cstdint>
+
+template<uint32_t BASE_ADDR>
+class pwm_regs {
+public:
+    BEGIN_BF_DECL(pwmcfg_t, uint32_t);
+        BF_FIELD(scale, 0, 4);
+        BF_FIELD(sticky, 8, 1);
+        BF_FIELD(zerocmp, 9, 1);
+        BF_FIELD(deglitch, 10, 1);
+        BF_FIELD(enalways, 12, 1);
+        BF_FIELD(enoneshot, 13, 1);
+        BF_FIELD(cmp0center, 16, 1);
+        BF_FIELD(cmp1center, 17, 1);
+        BF_FIELD(cmp2center, 18, 1);
+        BF_FIELD(cmp3center, 19, 1);
+        BF_FIELD(cmp0gang, 24, 1);
+        BF_FIELD(cmp1gang, 25, 1);
+        BF_FIELD(cmp2gang, 26, 1);
+        BF_FIELD(cmp3gang, 27, 1);
+        BF_FIELD(cmp0ip, 28, 1);
+        BF_FIELD(cmp1ip, 29, 1);
+        BF_FIELD(cmp2ip, 30, 1);
+        BF_FIELD(cmp3ip, 31, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(pwms_t, uint32_t);
+        BF_FIELD(s, 0, 16);
+    END_BF_DECL() r_pwms;
+
+    BEGIN_BF_DECL(pwmcmp0_t, uint32_t);
+        BF_FIELD(cmp0, 0, 16);
+    END_BF_DECL() r_pwmcmp0;
+
+    BEGIN_BF_DECL(pwmcmp1_t, uint32_t);
+        BF_FIELD(cmp0, 0, 16);
+    END_BF_DECL() r_pwmcmp1;
+
+    BEGIN_BF_DECL(pwmcmp2_t, uint32_t);
+        BF_FIELD(cmp0, 0, 16);
+    END_BF_DECL() r_pwmcmp2;
+
+    BEGIN_BF_DECL(pwmcmp3_t, uint32_t);
+        BF_FIELD(cmp0, 0, 16);
+    END_BF_DECL() r_pwmcmp3;
+
+    static inline pwmcfg_t& cfg_reg(){
+        return *reinterpret_cast<pwmcfg_t*>(BASE_ADDR+PWM_CFG);
+    }
+
+    static inline uint32_t& count_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+PWM_COUNT);
+    }
+
+    static inline pwms_t& s_reg(){
+        return *reinterpret_cast<pwms_t*>(BASE_ADDR+PWM_S);
+    }
+
+    static inline pwmcmp0_t& cmp0_reg(){
+        return *reinterpret_cast<pwmcmp0_t*>(BASE_ADDR+PWM_CMP0);
+    }
+
+    static inline pwmcmp1_t& cmp1_reg(){
+        return *reinterpret_cast<pwmcmp1_t*>(BASE_ADDR+PWM_CMP1);
+    }
+
+    static inline pwmcmp2_t& cmp2_reg(){
+        return *reinterpret_cast<pwmcmp2_t*>(BASE_ADDR+PWM_CMP2);
+    }
+
+    static inline pwmcmp3_t& cmp3_reg(){
+        return *reinterpret_cast<pwmcmp3_t*>(BASE_ADDR+PWM_CMP3);
+    }
+
+    static inline bool oneshot_delay(long delay_us){
+        auto scaling_factor=0;
+        while(delay_us/(1<<scaling_factor) > std::numeric_limits<unsigned short>::max()){
+            scaling_factor++;
+        }
+        cfg_reg()=0;
+        count_reg()=0;
+        cfg_reg().scale=4+scaling_factor; // divide by 16 so we get 1us per pwm clock
+        cmp0_reg().cmp0 = delay_us/(1<<scaling_factor);
+        pwm_active=true;
+        cfg_reg().enoneshot=true;
+        do{
+            asm("wfi");
+            asm("nop");
+        }while(pwm_active);
+        return true;
+    }
+
+    static void pwm_interrupt_handler(){
+        cfg_reg().cmp0ip=false;
+        pwm_active=false;
+    }
+
+    inline
+    static bool is_active(){ return pwm_active; }
+
+    inline
+    static void set_active() {pwm_active=true;}
+
+private:
+    static volatile bool pwm_active;
+};
+
+
+#endif /* PWM_H_ */

hifive1-vp/riscv-bldc-forced-commutation/src/io/spi.h

@@ -0,0 +1,200 @@
+/*
+ * spi.h
+ *
+ *  Created on: 29.07.2018
+ *      Author: eyck
+ */
+
+#ifndef SPI_H_
+#define SPI_H_
+
+#include <sifive/devices/spi.h>
+#include "util/bit_field.h"
+#include <array>
+#include <cstdint>
+
+template<uint32_t BASE_ADDR>
+class spi_regs {
+public:
+    // storage declarations
+    BEGIN_BF_DECL(sckdiv_t, uint32_t);
+        BF_FIELD(div, 0, 12);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(sckmode_t, uint32_t);
+        BF_FIELD(pha, 0, 1);
+        BF_FIELD(pol, 1, 1);
+    END_BF_DECL();
+
+    uint32_t r_csid;
+
+    uint32_t r_csdef;
+
+    BEGIN_BF_DECL(csmode_t, uint32_t);
+        BF_FIELD(mode, 0, 2);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(delay0_t, uint32_t);
+        BF_FIELD(cssck, 0, 8);
+        BF_FIELD(sckcs, 16, 8);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(delay1_t, uint32_t);
+        BF_FIELD(intercs, 0, 16);
+        BF_FIELD(interxfr, 16, 8);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(fmt_t, uint32_t);
+        BF_FIELD(proto, 0, 2);
+        BF_FIELD(endian, 2, 1);
+        BF_FIELD(dir, 3, 1);
+        BF_FIELD(len, 16, 4);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(txdata_t, uint32_t);
+        BF_FIELD(data, 0, 8);
+        BF_FIELD(full, 31, 1);
+    END_BF_DECL() r_txdata;
+
+    BEGIN_BF_DECL(rxdata_t, uint32_t);
+        BF_FIELD(data, 0, 8);
+        BF_FIELD(empty, 31, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(txmark_t, uint32_t);
+        BF_FIELD(txmark, 0, 3);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(rxmark_t, uint32_t);
+        BF_FIELD(rxmark, 0, 3);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(fctrl_t, uint32_t);
+        BF_FIELD(en, 0, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(ffmt_t, uint32_t);
+        BF_FIELD(cmd_en, 0, 1);
+        BF_FIELD(addr_len, 1, 2);
+        BF_FIELD(pad_cnt, 3, 4);
+        BF_FIELD(cmd_proto, 7, 2);
+        BF_FIELD(addr_proto, 9, 2);
+        BF_FIELD(data_proto, 11, 2);
+        BF_FIELD(cmd_code, 16, 8);
+        BF_FIELD(pad_code, 24, 8);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(ie_t, uint32_t);
+        BF_FIELD(txwm, 0, 1);
+        BF_FIELD(rxwm, 1, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(ip_t, uint32_t);
+        BF_FIELD(txwm, 0, 1);
+        BF_FIELD(rxwm, 1, 1);
+    END_BF_DECL();
+
+    static inline sckdiv_t& sckdiv_reg(){
+        return *reinterpret_cast<sckdiv_t*>(BASE_ADDR+SPI_REG_SCKDIV);
+    }
+
+    static inline sckmode_t& sckmode_reg(){
+        return *reinterpret_cast<sckmode_t*>(BASE_ADDR+SPI_REG_SCKMODE);
+    }
+
+    static inline uint32_t& csid_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_CSID);
+    }
+
+    static inline uint32_t& csdef_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_CSDEF);
+    }
+
+    static inline csmode_t& csmode_reg(){
+        return *reinterpret_cast<csmode_t*>(BASE_ADDR+SPI_REG_CSMODE);
+    }
+
+    static inline delay0_t& dcssck_reg(){
+        return *reinterpret_cast<delay0_t*>(BASE_ADDR+SPI_REG_DCSSCK);
+    }
+
+    static inline uint32_t& dsckcs_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_DSCKCS);
+    }
+
+    static inline delay1_t& dintercs_reg(){
+        return *reinterpret_cast<delay1_t*>(BASE_ADDR+SPI_REG_DINTERCS);
+    }
+
+    static inline uint32_t& dinterxfr_reg(){
+        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPI_REG_DINTERXFR);
+    }
+
+    static inline fmt_t& fmt_reg(){
+        return *reinterpret_cast<fmt_t*>(BASE_ADDR+SPI_REG_FMT);
+    }
+
+    static inline txdata_t& txfifo_reg(){
+        return *reinterpret_cast<txdata_t*>(BASE_ADDR+SPI_REG_TXFIFO);
+    }
+
+    static inline rxdata_t& rxfifo_reg(){
+        return *reinterpret_cast<rxdata_t*>(BASE_ADDR+SPI_REG_RXFIFO);
+    }
+
+    static inline txmark_t& txctrl_reg(){
+        return *reinterpret_cast<txmark_t*>(BASE_ADDR+SPI_REG_TXCTRL);
+    }
+
+    static inline rxmark_t& rxctrl_reg(){
+        return *reinterpret_cast<rxmark_t*>(BASE_ADDR+SPI_REG_RXCTRL);
+    }
+
+    static inline fctrl_t& fctrl_reg(){
+        return *reinterpret_cast<fctrl_t*>(BASE_ADDR+SPI_REG_FCTRL);
+    }
+
+    static inline ffmt_t& ffmt_reg(){
+        return *reinterpret_cast<ffmt_t*>(BASE_ADDR+SPI_REG_FFMT);
+    }
+
+    static inline ie_t& ie_reg(){
+        return *reinterpret_cast<ie_t*>(BASE_ADDR+SPI_REG_IE);
+    }
+
+    static inline ip_t& ip_reg(){
+        return *reinterpret_cast<ip_t*>(BASE_ADDR+SPI_REG_IP);
+    }
+
+    template<size_t SIZE>
+    static bool transfer(std::array<uint8_t, SIZE>& bytes){
+        csmode_reg().mode=2; // HOLD mode
+        rxctrl_reg().rxmark=bytes.size()-1; // trigger irq if more than 2 bytes are received;
+        ie_reg().rxwm=1;
+        // write data bytes
+        for(size_t i=0; i<bytes.size(); ++i)
+            txfifo_reg()=bytes[i];
+        // wait until SPI is done
+        spi_active=true;
+        do{
+            asm("wfi");
+            asm("nop");
+        }while(spi_active);
+        // deactivate SPI
+        csmode_reg().mode=0; // AUTO mode, deactivates CS
+        // fetch results
+        for(size_t i=0; i<bytes.size(); ++i) bytes[i]=rxfifo_reg();
+        return true;
+    }
+
+    static void spi_rx_interrupt_handler(){
+        ip_reg().rxwm=0;
+        ie_reg().rxwm=0;
+        spi_active=false;
+    }
+
+private:
+    static volatile bool spi_active;
+};
+
+#endif /* SPI_H_ */

hifive1-vp/riscv-bldc-forced-commutation/src/io/uart.h

@@ -0,0 +1,83 @@
+/*
+ * spi.h
+ *
+ *  Created on: 29.07.2018
+ *      Author: eyck
+ */
+
+#ifndef UART_H_
+#define UART_H_
+
+#include <sifive/devices/uart.h>
+#include "util/bit_field.h"
+#include <cstdint>
+
+template<uint32_t BASE_ADDR>
+class uart_regs {
+public:
+    BEGIN_BF_DECL(txdata_t, uint32_t);
+        BF_FIELD(data, 0, 8);
+        BF_FIELD(full, 31, 1);
+    END_BF_DECL() ;
+
+    BEGIN_BF_DECL(rxdata_t, uint32_t);
+        BF_FIELD(data, 0, 8);
+        BF_FIELD(empty, 31, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(txctrl_t, uint32_t);
+        BF_FIELD(txen, 0, 1);
+        BF_FIELD(nstop, 1, 1);
+        BF_FIELD(txcnt, 16, 3);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(rxctrl_t, uint32_t);
+        BF_FIELD(rxen, 0, 1);
+        BF_FIELD(rxcnt, 16, 3);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(ie_t, uint32_t);
+        BF_FIELD(txwm, 0, 1);
+        BF_FIELD(rxwm, 1, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(ip_t, uint32_t);
+        BF_FIELD(txwm, 0, 1);
+        BF_FIELD(rxwm, 1, 1);
+    END_BF_DECL();
+
+    BEGIN_BF_DECL(div_t, uint32_t);
+        BF_FIELD(div, 0, 16);
+    END_BF_DECL();
+
+    static inline txdata_t& txdata_reg(){
+        return *reinterpret_cast<txdata_t*>(BASE_ADDR+UART_REG_TXFIFO);
+    }
+
+    static inline rxdata_t& rxdata_reg(){
+        return *reinterpret_cast<rxdata_t*>(BASE_ADDR+UART_REG_RXFIFO);
+    }
+
+    static inline txctrl_t& txctrl_reg(){
+        return *reinterpret_cast<txctrl_t*>(BASE_ADDR+UART_REG_TXCTRL);
+    }
+
+    static inline rxctrl_t& rxctrl_reg(){
+        return *reinterpret_cast<rxctrl_t*>(BASE_ADDR+UART_REG_RXCTRL);
+    }
+
+    static inline ie_t& ie_reg(){
+        return *reinterpret_cast<ie_t*>(BASE_ADDR+UART_REG_IE);
+    }
+
+    static inline ip_t& ip_reg(){
+        return *reinterpret_cast<ip_t*>(BASE_ADDR+UART_REG_IP);
+    }
+
+    static inline div_t& div_reg(){
+        return *reinterpret_cast<div_t*>(BASE_ADDR+UART_REG_DIV);
+    }
+
+};
+
+#endif /* SPI_H_ */