Working version
This commit is contained in:
parent
a4bfa4e679
commit
2ebe9541d5
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@ -5,11 +5,11 @@ C_SRCS = $(wildcard *.c)
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#CFLAGS += -O2
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BOARD=freedom-e300-hifive1
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LINK_TARGET=link
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LINK_TARGET=flash
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RISCV_ARCH=rv32imac
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RISCV_ABI=ilp32
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LDFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany
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LDFLAGS = -Wl,--wrap=printf -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany
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TOOL_DIR?=/opt/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin
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BSP_BASE = ./bsp
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@ -0,0 +1,163 @@
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// See LICENSE for license details.
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#include "sifive/devices/clic.h"
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#include "clic/clic_driver.h"
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#include "platform.h"
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#include "encoding.h"
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#include <string.h>
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void volatile_memzero(uint8_t * base, unsigned int size) {
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volatile uint8_t * ptr;
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for (ptr = base; ptr < (base + size); ptr++){
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*ptr = 0;
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}
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}
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// Note that there are no assertions or bounds checking on these
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// parameter values.
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void clic_init (
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clic_instance_t * this_clic,
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uintptr_t hart_addr,
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interrupt_function_ptr_t* vect_table,
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interrupt_function_ptr_t default_handler,
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uint32_t num_irq,
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uint32_t num_config_bits
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)
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{
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this_clic->hart_addr= hart_addr;
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this_clic->vect_table= vect_table;
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this_clic->num_config_bits= num_config_bits;
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//initialize vector table
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for(int i=0;i++;i<num_irq) {
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this_clic->vect_table[i] = default_handler;
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}
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//set base vectors
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write_csr(mtvt, vect_table);
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//clear all interrupt enables and pending
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volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIE), num_irq);
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volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIP), num_irq);
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//clear nlbits and nvbits; all interrupts trap to level 15
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG)=0;
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}
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void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler) {
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this_clic->vect_table[source] = handler;
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}
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void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source) {
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 1;
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}
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void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 0;
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}
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void clic_set_pending(clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 1;
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}
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void clic_clear_pending(clic_instance_t * this_clic, uint32_t source){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 0;
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}
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void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source) = intcfg;
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}
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uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source){
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return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source);
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}
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void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg){
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*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG) = cfg;
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}
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uint8_t clic_get_cliccfg (clic_instance_t * this_clic){
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return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG);
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}
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//sets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level) {
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift level right to mask off unused bits
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level = level>>((this_clic->num_config_bits)-nlbits); //plus this_clic->nmbits which is always 0 for now.
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//shift level into correct bit position
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level = level << (8-this_clic->num_config_bits) + (this_clic->num_config_bits - nlbits);
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//write to clicintcfg
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uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
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clic_set_intcfg(this_clic, source, (current_intcfg | level));
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return level;
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}
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//gets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source) {
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uint8_t level;
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level = clic_get_intcfg(this_clic, source);
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift level
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level = level >> (8-(this_clic->num_config_bits));
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//shift level right to mask off priority bits
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level = level>>(this_clic->num_config_bits-nlbits); //this_clic->nmbits which is always 0 for now.
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return level;
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}
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority) {
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//priority bits = num_config_bits - nlbits
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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uint8_t priority_bits = this_clic->num_config_bits-nlbits;
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if(priority_bits = 0) {
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//no bits to set
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return 0;
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}
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//mask off unused bits
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priority = priority >> (8-priority_bits);
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//shift into the correct bit position
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priority = priority << (8-(this_clic->num_config_bits));
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//write to clicintcfg
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uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
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clic_set_intcfg(this_clic, source, (current_intcfg | priority));
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return current_intcfg;
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}
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//gets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source) {
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uint8_t priority;
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priority = clic_get_intcfg(this_clic, source);
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//extract nlbits
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uint8_t nlbits = clic_get_cliccfg(this_clic);
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nlbits = (nlbits >>1) & 0x7;
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//shift left to mask off level bits
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priority = priority << nlbits;
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//shift priority
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priority = priority >> (8-((this_clic->num_config_bits)+nlbits));
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return priority;
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}
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@ -0,0 +1,44 @@
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// See LICENSE file for licence details
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#ifndef PLIC_DRIVER_H
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#define PLIC_DRIVER_H
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__BEGIN_DECLS
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#include "platform.h"
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typedef void (*interrupt_function_ptr_t) (void);
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typedef struct __clic_instance_t
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{
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uintptr_t hart_addr;
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interrupt_function_ptr_t* vect_table;
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uint32_t num_config_bits;
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uint32_t num_sources;
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} clic_instance_t;
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// Note that there are no assertions or bounds checking on these
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// parameter values.
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void clic_init (clic_instance_t * this_clic, uintptr_t hart_addr, interrupt_function_ptr_t* vect_table, interrupt_function_ptr_t default_handler, uint32_t num_irq,uint32_t num_config_bits);
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void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler);
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void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source);
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void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source);
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void clic_set_pending(clic_instance_t * this_clic, uint32_t source);
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void clic_clear_pending(clic_instance_t * this_clic, uint32_t source);
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void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg);
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uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source);
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void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg);
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uint8_t clic_get_cliccfg (clic_instance_t * this_clic);
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//sets an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level);
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//get an interrupt level based encoding of nmbits, nlbits
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uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source);
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority);
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//sets an interrupt priority based encoding of nmbits, nlbits
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uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source);
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__END_DECLS
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#endif
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@ -2,7 +2,7 @@
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#include "platform.h"
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#ifdef PRCI_BASE_ADDR
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#ifdef PRCI_CTRL_ADDR
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#include "fe300prci/fe300prci_driver.h"
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#include <unistd.h>
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@ -0,0 +1,161 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY( _start )
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MEMORY
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{
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flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
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}
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PHDRS
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{
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flash PT_LOAD;
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ram_init PT_LOAD;
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ram PT_NULL;
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}
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SECTIONS
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{
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__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
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.init :
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{
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KEEP (*(SORT_NONE(.init)))
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} >flash AT>flash :flash
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.text :
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{
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*(.text.unlikely .text.unlikely.*)
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*(.text.startup .text.startup.*)
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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} >flash AT>flash :flash
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.fini :
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{
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KEEP (*(SORT_NONE(.fini)))
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} >flash AT>flash :flash
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} >flash AT>flash :flash
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. = ALIGN(4);
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >flash AT>flash :flash
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >flash AT>flash :flash
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >flash AT>flash :flash
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
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doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >flash AT>flash :flash
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >flash AT>flash :flash
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.lalign :
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{
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. = ALIGN(4);
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PROVIDE( _data_lma = . );
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} >flash AT>flash :flash
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE( _data = . );
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} >ram AT>flash :ram_init
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.data :
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{
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||||
*(.data .data.*)
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*(.gnu.linkonce.d.*)
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||||
. = ALIGN(8);
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||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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||||
. = ALIGN(8);
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||||
*(.srodata.cst16)
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||||
*(.srodata.cst8)
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*(.srodata.cst4)
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||||
*(.srodata.cst2)
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||||
*(.srodata .srodata.*)
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||||
} >ram AT>flash :ram_init
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. = ALIGN(4);
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||||
PROVIDE( _edata = . );
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PROVIDE( edata = . );
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||||
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||||
PROVIDE( _fbss = . );
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PROVIDE( __bss_start = . );
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.bss :
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{
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||||
*(.sbss*)
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||||
*(.gnu.linkonce.sb.*)
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||||
*(.bss .bss.*)
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||||
*(.gnu.linkonce.b.*)
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||||
*(COMMON)
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||||
. = ALIGN(4);
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||||
} >ram AT>ram :ram
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||||
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||||
. = ALIGN(8);
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||||
PROVIDE( _end = . );
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||||
PROVIDE( end = . );
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||||
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||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
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||||
{
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||||
PROVIDE( _heap_end = . );
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||||
. = __stack_size;
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||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
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||||
}
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||||
|
|
@ -0,0 +1,98 @@
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|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
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#include <stdio.h>
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#include <unistd.h>
|
||||
|
||||
#include "platform.h"
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||||
#include "encoding.h"
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||||
|
||||
#define CPU_FREQ 32000000
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||||
#define XSTR(x) #x
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#define STR(x) XSTR(x)
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||||
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||||
extern int main(int argc, char** argv);
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||||
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||||
unsigned long get_cpu_freq()
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{
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||||
return CPU_FREQ;
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||||
}
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||||
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||||
unsigned long get_timer_freq()
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||||
{
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||||
return get_cpu_freq();
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||||
}
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||||
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||||
uint64_t get_timer_value()
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||||
{
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||||
#if __riscv_xlen == 32
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||||
while (1) {
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||||
uint32_t hi = read_csr(mcycleh);
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||||
uint32_t lo = read_csr(mcycle);
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||||
if (hi == read_csr(mcycleh))
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return ((uint64_t)hi << 32) | lo;
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}
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#else
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return read_csr(mcycle);
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||||
#endif
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||||
}
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||||
|
||||
static void uart_init(size_t baud_rate)
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||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1;
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||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
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||||
}
|
||||
|
||||
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typedef void (*interrupt_function_ptr_t) (void);
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interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
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||||
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||||
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void trap_entry(void) __attribute__((interrupt, aligned(64)));
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||||
void trap_entry(void)
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||||
{
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||||
unsigned long mcause = read_csr(mcause);
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||||
unsigned long mepc = read_csr(mepc);
|
||||
if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
} else {
|
||||
while(1);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CLIC_DIRECT
|
||||
#else
|
||||
void default_handler(void)__attribute__((interrupt));;
|
||||
#endif
|
||||
void default_handler(void)
|
||||
{
|
||||
puts("default handler\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
//initialize vector table
|
||||
int i=0;
|
||||
while(i<CLIC_NUM_INTERRUPTS) {
|
||||
localISR[i++] = default_handler;
|
||||
}
|
||||
|
||||
write_csr(mtvt, localISR);
|
||||
|
||||
#ifdef CLIC_DIRECT
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC_VECT));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#define MTVEC_DIRECT 0X00
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define MTVEC_CLIC_VECT 0X03
|
||||
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/clic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define CLIC_HART0_ADDR _AC(0x02800000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
|
||||
#define CLIC0_REG8(offset) (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define CLIC_NUM_INTERRUPTS 28 + 16
|
||||
|
||||
#ifdef E20
|
||||
#define CLIC_CONFIG_BITS 2
|
||||
#else
|
||||
#define CLIC_CONFIG_BITS 4
|
||||
#endif
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x80008000, LENGTH = 32K
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_COREPLEXIP_ARTY_H
|
||||
#define _SIFIVE_COREPLEXIP_ARTY_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* GPIO Connections
|
||||
*****************************************************************************/
|
||||
|
||||
// These are the GPIO bit offsets for the directly driven
|
||||
// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit.
|
||||
// Additional RGB LEDs are driven by the 3 PWM outputs.
|
||||
|
||||
#define RED_LED_OFFSET 0
|
||||
#define GREEN_LED_OFFSET 1
|
||||
#define BLUE_LED_OFFSET 2
|
||||
|
||||
// Switch 3 is used as a GPIO input. (Switch 0 is used to set
|
||||
// the reset vector, the other switches are unused).
|
||||
|
||||
#define SW_3_OFFSET 3
|
||||
|
||||
// These are the buttons which are mapped as inputs.
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#define BUTTON_0_OFFSET 4
|
||||
#define BUTTON_1_OFFSET 5
|
||||
#define BUTTON_2_OFFSET 6
|
||||
#define BUTTON_3_OFFSET 7
|
||||
|
||||
// These are the bit offsets for the different GPIO pins
|
||||
// mapped onto the PMOD A header.
|
||||
|
||||
#define JA_0_OFFSET 8
|
||||
#define JA_1_OFFSET 9
|
||||
#define JA_2_OFFSET 10
|
||||
#define JA_3_OFFSET 11
|
||||
#define JA_4_OFFSET 12
|
||||
#define JA_5_OFFSET 13
|
||||
#define JA_6_OFFSET 14
|
||||
#define JA_7_OFFSET 15
|
||||
|
||||
// The below gives a mapping between global interrupt
|
||||
// sources and their number. Note that on the coreplex
|
||||
// deliverable, the io_global_interrupts go directly into
|
||||
// the PLIC. The evaluation image on the FPGA mimics a
|
||||
// system with peripheral devices which are driving the
|
||||
// global interrupt lines.
|
||||
// So, on this image, in order to get an interrupt from
|
||||
// e.g. pressing BUTTON_0:
|
||||
// 1) Steps which are external to the delivery coreplex:
|
||||
// a) The corresponding GPIO pin must be configured as in input
|
||||
// b) The "interrupt on fall" bit must be set for the GPIO pin
|
||||
// 2) Steps which would also need to be performed for the delivery coreplex:
|
||||
// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC.
|
||||
// b) The external interrupt bit must be enabled in MSTATUS
|
||||
// c) Interrupts must be enabled globally in the core.
|
||||
|
||||
// Any of the above GPIO pins can be used as global interrupt
|
||||
// sources by adding their offset to the INT_GPIO_BASE.
|
||||
// For example, the buttons are shown here:
|
||||
|
||||
#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET)
|
||||
#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET)
|
||||
|
||||
// In addition, the Switches are mapped directly to
|
||||
// the PLIC (without going through the GPIO Peripheral).
|
||||
|
||||
#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0)
|
||||
#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1)
|
||||
#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2)
|
||||
#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3)
|
||||
|
||||
// This gives the mapping from inputs to LOCAL interrupts.
|
||||
|
||||
#define LOCAL_INT_SW_0 0
|
||||
#define LOCAL_INT_SW_1 1
|
||||
#define LOCAL_INT_SW_2 2
|
||||
#define LOCAL_INT_SW_3 3
|
||||
#define LOCAL_INT_BTN_0 4
|
||||
#define LOCAL_INT_BTN_1 5
|
||||
#define LOCAL_INT_BTN_2 6
|
||||
#define LOCAL_INT_BTN_3 7
|
||||
#define LOCAL_INT_JA_0 8
|
||||
#define LOCAL_INT_JA_1 9
|
||||
#define LOCAL_INT_JA_2 10
|
||||
#define LOCAL_INT_JA_3 11
|
||||
#define LOCAL_INT_JA_4 12
|
||||
#define LOCAL_INT_JA_5 13
|
||||
#define LOCAL_INT_JA_6 14
|
||||
#define LOCAL_INT_JA_7 15
|
||||
|
||||
#define RTC_FREQ 32768
|
||||
|
||||
void write_hex(int fd, unsigned long int hex);
|
||||
|
||||
#endif /* _SIFIVE_COREPLEXIP_ARTY_H */
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
#define CPU_FREQ 65000000
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
#define TRAP_ENTRY trap_entry
|
||||
#else
|
||||
#define TRAP_ENTRY vtrap_entry
|
||||
#endif
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void TRAP_ENTRY();
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
return CPU_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_LOCAL_ISR
|
||||
typedef void (*my_interrupt_function_ptr_t) (void);
|
||||
extern my_interrupt_function_ptr_t localISR[];
|
||||
#endif
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline));
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
#ifdef USE_LOCAL_ISR
|
||||
} else if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "Unhandled Trap:\n", 16);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_CLIC
|
||||
void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
|
||||
void trap_entry(void)
|
||||
{
|
||||
unsigned long mcause = read_csr(mcause);
|
||||
unsigned long mepc = read_csr(mepc);
|
||||
handle_trap(mcause, mepc);
|
||||
}
|
||||
#endif
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
#ifdef USE_CLIC
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#ifdef VECT_IRQ
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#else
|
||||
#define MTVEC_VECTORED 0x00
|
||||
#endif
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define IRQ_M_LOCAL 16
|
||||
#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x))
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
// Bulk set bits in `reg` to either 0 or 1.
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 28
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
flash PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >flash AT>flash :flash
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
//See LICENSE for license details.
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
#define CPU_FREQ 65000000
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
#define TRAP_ENTRY trap_entry
|
||||
#else
|
||||
#define TRAP_ENTRY vtrap_entry
|
||||
#endif
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void TRAP_ENTRY();
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
return CPU_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return get_cpu_freq();
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
while (1) {
|
||||
uint32_t hi = read_csr(mcycleh);
|
||||
uint32_t lo = read_csr(mcycle);
|
||||
if (hi == read_csr(mcycleh))
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
return read_csr(mcycle);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_LOCAL_ISR
|
||||
typedef void (*my_interrupt_function_ptr_t) (void);
|
||||
extern my_interrupt_function_ptr_t localISR[];
|
||||
#endif
|
||||
|
||||
#ifndef VECT_IRQ
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline));
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
#ifdef USE_LOCAL_ISR
|
||||
} else if (mcause & MCAUSE_INT) {
|
||||
localISR[mcause & MCAUSE_CAUSE] ();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "Unhandled Trap:\n", 16);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_CLIC
|
||||
void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
|
||||
void trap_entry(void)
|
||||
{
|
||||
unsigned long mcause = read_csr(mcause);
|
||||
unsigned long mepc = read_csr(mepc);
|
||||
handle_trap(mcause, mepc);
|
||||
}
|
||||
#endif
|
||||
|
||||
void _init()
|
||||
{
|
||||
#ifndef NO_INIT
|
||||
uart_init(115200);
|
||||
|
||||
puts("core freq at " STR(CPU_FREQ) " Hz\n");
|
||||
|
||||
#ifdef USE_CLIC
|
||||
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
|
||||
#else
|
||||
write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# JTAG adapter setup
|
||||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
|
||||
ftdi_vid_pid 0x15ba 0x002a
|
||||
|
||||
ftdi_layout_init 0x0808 0x0a1b
|
||||
ftdi_layout_signal nSRST -oe 0x0200
|
||||
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal LED -data 0x0800
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
# Un-comment these two flash lines if you have a SPI flash and want to write
|
||||
# it.
|
||||
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
|
||||
init
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
echo "Ready for Remote Connections"
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
#define MCAUSE_INT 0x80000000UL
|
||||
#define MCAUSE_CAUSE 0x000003FFUL
|
||||
#else
|
||||
#define MCAUSE_INT 0x8000000000000000UL
|
||||
#define MCAUSE_CAUSE 0x00000000000003FFUL
|
||||
#endif
|
||||
|
||||
#ifdef VECT_IRQ
|
||||
#define MTVEC_VECTORED 0x01
|
||||
#else
|
||||
#define MTVEC_VECTORED 0x00
|
||||
#endif
|
||||
#define MTVEC_CLIC 0x02
|
||||
#define IRQ_M_LOCAL 16
|
||||
#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x))
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
|
||||
#define RAM_MEM_ADDR _AC(0x80000000,UL)
|
||||
#define RAM_MEM_SIZE _AC(0x10000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
|
||||
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
|
||||
|
||||
// IOF masks
|
||||
|
||||
// Interrupt numbers
|
||||
#define RESERVED_INT_BASE 0
|
||||
#define UART0_INT_BASE 1
|
||||
#define EXTERNAL_INT_BASE 2
|
||||
#define SPI0_INT_BASE 6
|
||||
#define GPIO_INT_BASE 7
|
||||
#define PWM0_INT_BASE 23
|
||||
|
||||
// Helper functions
|
||||
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
|
||||
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
|
||||
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
|
||||
// Bulk set bits in `reg` to either 0 or 1.
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
|
||||
// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
|
||||
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
|
||||
#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
|
||||
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
|
||||
#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset)
|
||||
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#define NUM_GPIO 16
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 28
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#define HAS_BOARD_BUTTONS
|
||||
|
||||
#include "coreplexip-arty.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
ENTRY( _start )
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
ram PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
||||
PROVIDE( _fbss = . );
|
||||
PROVIDE( __bss_start = . );
|
||||
.bss :
|
||||
{
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
} >ram AT>ram :ram
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _end = . );
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
PROVIDE( _heap_end = . );
|
||||
} >ram AT>ram :ram
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv64imac
|
||||
RISCV_ABI := lp64
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.weak trap_entry
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
addi sp, sp, -32*REGBYTES
|
||||
|
|
|
|||
|
|
@ -120,11 +120,11 @@ SECTIONS
|
|||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.srodata :
|
||||
{
|
||||
PROVIDE( _gp = . + 0x800 );
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
|
|
@ -132,12 +132,6 @@ SECTIONS
|
|||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
|
@ -20,21 +20,21 @@
|
|||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
|
||||
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_BASE_ADDR _AC(0x10000000,UL)
|
||||
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_BASE_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_BASE_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_CTRL_ADDR _AC(0x10000000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_BASE_ADDR _AC(0x80000000,UL)
|
||||
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF Mappings
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
|
|
@ -91,20 +91,19 @@
|
|||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
|
||||
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
||||
|
|
@ -4,9 +4,8 @@ ENTRY( _start )
|
|||
|
||||
MEMORY
|
||||
{
|
||||
/*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/
|
||||
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
PHDRS
|
||||
|
|
@ -42,13 +41,6 @@ SECTIONS
|
|||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >flash AT>flash :flash
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
.preinit_array :
|
||||
|
|
@ -119,13 +111,16 @@ SECTIONS
|
|||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.srodata :
|
||||
{
|
||||
PROVIDE( _gp = . + 0x800 );
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
|
|
@ -133,12 +128,6 @@ SECTIONS
|
|||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
|
@ -120,11 +120,11 @@ SECTIONS
|
|||
{
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.srodata :
|
||||
{
|
||||
PROVIDE( _gp = . + 0x800 );
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
|
|
@ -132,12 +132,6 @@ SECTIONS
|
|||
*(.srodata .srodata.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
} >ram AT>flash :ram_init
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = . );
|
||||
PROVIDE( edata = . );
|
||||
|
|
@ -10,14 +10,14 @@ extern void trap_entry();
|
|||
|
||||
static unsigned long mtime_lo(void)
|
||||
{
|
||||
return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME);
|
||||
return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
|
||||
}
|
||||
|
||||
#ifdef __riscv32
|
||||
|
||||
static uint32_t mtime_hi(void)
|
||||
{
|
||||
return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4);
|
||||
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
|
|
|
|||
|
|
@ -23,25 +23,25 @@
|
|||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
|
||||
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
|
||||
#define OTP_MMAP_ADDR _AC(0x00020000,UL)
|
||||
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_BASE_ADDR _AC(0x10000000,UL)
|
||||
#define PRCI_BASE_ADDR _AC(0x10008000,UL)
|
||||
#define OTP_BASE_ADDR _AC(0x10010000,UL)
|
||||
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_BASE_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_BASE_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_BASE_ADDR _AC(0x80000000,UL)
|
||||
#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
|
||||
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
|
||||
#define OTP_MEM_ADDR _AC(0x00020000,UL)
|
||||
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_CTRL_ADDR _AC(0x10000000,UL)
|
||||
#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
|
||||
#define OTP_CTRL_ADDR _AC(0x10010000,UL)
|
||||
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MEM_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF masks
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
|
|
@ -100,20 +100,20 @@
|
|||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
|
||||
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# Describes the CPU on this board to the rest of the SDK.
|
||||
RISCV_ARCH := rv32imac
|
||||
RISCV_ABI := ilp32
|
||||
|
|
@ -76,6 +76,6 @@
|
|||
|
||||
#define RTC_FREQ 32768
|
||||
|
||||
void write_hex(int fd, uint32_t hex);
|
||||
void write_hex(int fd, unsigned long int hex);
|
||||
|
||||
#endif /* _SIFIVE_HIFIVE1_H */
|
||||
|
|
|
|||
|
|
@ -1,238 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "encoding.h"
|
||||
|
||||
extern int main(int argc, char** argv);
|
||||
extern void trap_entry();
|
||||
|
||||
static unsigned long mtime_lo(void)
|
||||
{
|
||||
return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME);
|
||||
}
|
||||
|
||||
#ifdef __riscv32
|
||||
|
||||
static uint32_t mtime_hi(void)
|
||||
{
|
||||
return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4);
|
||||
}
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
while (1) {
|
||||
uint32_t hi = mtime_hi();
|
||||
uint32_t lo = mtime_lo();
|
||||
if (hi == mtime_hi())
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* __riscv32 */
|
||||
|
||||
uint64_t get_timer_value()
|
||||
{
|
||||
return mtime_lo();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
unsigned long get_timer_freq()
|
||||
{
|
||||
return 32768;
|
||||
}
|
||||
|
||||
static void use_hfrosc(int div, int trim)
|
||||
{
|
||||
// Make sure the HFROSC is running at its default setting
|
||||
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
|
||||
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
|
||||
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
|
||||
}
|
||||
|
||||
static void use_pll(int refsel, int bypass, int r, int f, int q)
|
||||
{
|
||||
// Ensure that we aren't running off the PLL before we mess with it.
|
||||
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
|
||||
// Make sure the HFROSC is running at its default setting
|
||||
use_hfrosc(4, 16);
|
||||
}
|
||||
|
||||
// Set PLL Source to be HFXOSC if available.
|
||||
uint32_t config_value = 0;
|
||||
|
||||
config_value |= PLL_REFSEL(refsel);
|
||||
|
||||
if (bypass) {
|
||||
// Bypass
|
||||
config_value |= PLL_BYPASS(1);
|
||||
|
||||
PRCI_REG(PRCI_PLLCFG) = config_value;
|
||||
|
||||
// If we don't have an HFXTAL, this doesn't really matter.
|
||||
// Set our Final output divide to divide-by-1:
|
||||
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
|
||||
} else {
|
||||
// In case we are executing from QSPI,
|
||||
// (which is quite likely) we need to
|
||||
// set the QSPI clock divider appropriately
|
||||
// before boosting the clock frequency.
|
||||
|
||||
// Div = f_sck/2
|
||||
SPI0_REG(SPI_REG_SCKDIV) = 8;
|
||||
|
||||
// Set DIV Settings for PLL
|
||||
// Both HFROSC and HFXOSC are modeled as ideal
|
||||
// 16MHz sources (assuming dividers are set properly for
|
||||
// HFROSC).
|
||||
// (Legal values of f_REF are 6-48MHz)
|
||||
|
||||
// Set DIVR to divide-by-2 to get 8MHz frequency
|
||||
// (legal values of f_R are 6-12 MHz)
|
||||
|
||||
config_value |= PLL_BYPASS(1);
|
||||
config_value |= PLL_R(r);
|
||||
|
||||
// Set DIVF to get 512Mhz frequncy
|
||||
// There is an implied multiply-by-2, 16Mhz.
|
||||
// So need to write 32-1
|
||||
// (legal values of f_F are 384-768 MHz)
|
||||
config_value |= PLL_F(f);
|
||||
|
||||
// Set DIVQ to divide-by-2 to get 256 MHz frequency
|
||||
// (legal values of f_Q are 50-400Mhz)
|
||||
config_value |= PLL_Q(q);
|
||||
|
||||
// Set our Final output divide to divide-by-1:
|
||||
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
|
||||
|
||||
PRCI_REG(PRCI_PLLCFG) = config_value;
|
||||
|
||||
// Un-Bypass the PLL.
|
||||
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
|
||||
|
||||
// Wait for PLL Lock
|
||||
// Note that the Lock signal can be glitchy.
|
||||
// Need to wait 100 us
|
||||
// RTC is running at 32kHz.
|
||||
// So wait 4 ticks of RTC.
|
||||
uint32_t now = mtime_lo();
|
||||
while (mtime_lo() - now < 4) ;
|
||||
|
||||
// Now it is safe to check for PLL Lock
|
||||
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
|
||||
}
|
||||
|
||||
// Switch over to PLL Clock source
|
||||
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
|
||||
}
|
||||
|
||||
static void use_default_clocks()
|
||||
{
|
||||
// Turn off the LFROSC
|
||||
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
|
||||
|
||||
// Use HFROSC
|
||||
use_hfrosc(4, 16);
|
||||
}
|
||||
|
||||
static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
|
||||
{
|
||||
unsigned long start_mtime, delta_mtime;
|
||||
unsigned long mtime_freq = get_timer_freq();
|
||||
|
||||
// Don't start measuruing until we see an mtime tick
|
||||
unsigned long tmp = mtime_lo();
|
||||
do {
|
||||
start_mtime = mtime_lo();
|
||||
} while (start_mtime == tmp);
|
||||
|
||||
unsigned long start_mcycle = read_csr(mcycle);
|
||||
|
||||
do {
|
||||
delta_mtime = mtime_lo() - start_mtime;
|
||||
} while (delta_mtime < n);
|
||||
|
||||
unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
|
||||
|
||||
return (delta_mcycle / delta_mtime) * mtime_freq
|
||||
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
|
||||
}
|
||||
|
||||
unsigned long get_cpu_freq()
|
||||
{
|
||||
static uint32_t cpu_freq;
|
||||
|
||||
if (!cpu_freq) {
|
||||
// warm up I$
|
||||
measure_cpu_freq(1);
|
||||
// measure for real
|
||||
cpu_freq = measure_cpu_freq(10);
|
||||
}
|
||||
|
||||
return cpu_freq;
|
||||
}
|
||||
|
||||
static void uart_init(size_t baud_rate)
|
||||
{
|
||||
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
|
||||
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
|
||||
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
|
||||
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifdef USE_PLIC
|
||||
extern void handle_m_ext_interrupt();
|
||||
#endif
|
||||
|
||||
#ifdef USE_M_TIME
|
||||
extern void handle_m_time_interrupt();
|
||||
#endif
|
||||
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
|
||||
{
|
||||
if (0){
|
||||
#ifdef USE_PLIC
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
|
||||
handle_m_ext_interrupt();
|
||||
#endif
|
||||
#ifdef USE_M_TIME
|
||||
// External Machine-Level interrupt from PLIC
|
||||
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
|
||||
handle_m_time_interrupt();
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
write(1, "trap\n", 5);
|
||||
_exit(1 + mcause);
|
||||
}
|
||||
return epc;
|
||||
}
|
||||
|
||||
void _init()
|
||||
{
|
||||
|
||||
#ifndef NO_INIT
|
||||
use_default_clocks();
|
||||
use_pll(0, 0, 1, 31, 1);
|
||||
uart_init(115200);
|
||||
|
||||
printf("core freq at %d Hz\n", get_cpu_freq());
|
||||
|
||||
write_csr(mtvec, &trap_entry);
|
||||
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
|
||||
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
|
||||
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void _fini()
|
||||
{
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
adapter_khz 10000
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Dual RS232-HS"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x001b
|
||||
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
|
||||
|
||||
#Reset Stretcher logic on FE310 is ~1 second long
|
||||
#This doesn't apply if you use
|
||||
# ftdi_set_signal, but still good to document
|
||||
#adapter_nsrst_delay 1500
|
||||
|
||||
set _CHIPNAME riscv
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||||
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
|
||||
|
||||
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
|
||||
init
|
||||
#reset -- This type of reset is not implemented yet
|
||||
if {[ info exists pulse_srst]} {
|
||||
ftdi_set_signal nSRST 0
|
||||
ftdi_set_signal nSRST z
|
||||
#Wait for the reset stretcher
|
||||
#It will work without this, but
|
||||
#will incur lots of delays for later commands.
|
||||
sleep 1500
|
||||
}
|
||||
halt
|
||||
#flash protect 0 64 last off
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PLATFORM_H
|
||||
#define _SIFIVE_PLATFORM_H
|
||||
|
||||
// Some things missing from the official encoding.h
|
||||
#define MCAUSE_INT 0x80000000
|
||||
#define MCAUSE_CAUSE 0x7FFFFFFF
|
||||
|
||||
#include "sifive/const.h"
|
||||
#include "sifive/devices/aon.h"
|
||||
#include "sifive/devices/clint.h"
|
||||
#include "sifive/devices/gpio.h"
|
||||
#include "sifive/devices/otp.h"
|
||||
#include "sifive/devices/plic.h"
|
||||
#include "sifive/devices/prci.h"
|
||||
#include "sifive/devices/pwm.h"
|
||||
#include "sifive/devices/spi.h"
|
||||
#include "sifive/devices/uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Platform definitions
|
||||
*****************************************************************************/
|
||||
|
||||
// Memory map
|
||||
#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
|
||||
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
|
||||
#define OTP_MMAP_ADDR _AC(0x00020000,UL)
|
||||
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
|
||||
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
|
||||
#define AON_BASE_ADDR _AC(0x10000000,UL)
|
||||
#define PRCI_BASE_ADDR _AC(0x10008000,UL)
|
||||
#define OTP_BASE_ADDR _AC(0x10010000,UL)
|
||||
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
|
||||
#define UART0_BASE_ADDR _AC(0x10013000,UL)
|
||||
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
|
||||
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
|
||||
#define UART1_BASE_ADDR _AC(0x10023000,UL)
|
||||
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
|
||||
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
|
||||
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
|
||||
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
|
||||
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
|
||||
#define MEM_BASE_ADDR _AC(0x80000000,UL)
|
||||
|
||||
// IOF masks
|
||||
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
|
||||
#define SPI11_NUM_SS (4)
|
||||
#define IOF_SPI1_SS0 (2u)
|
||||
#define IOF_SPI1_SS1 (8u)
|
||||
#define IOF_SPI1_SS2 (9u)
|
||||
#define IOF_SPI1_SS3 (10u)
|
||||
#define IOF_SPI1_MOSI (3u)
|
||||
#define IOF_SPI1_MISO (4u)
|
||||
#define IOF_SPI1_SCK (5u)
|
||||
#define IOF_SPI1_DQ0 (3u)
|
||||
#define IOF_SPI1_DQ1 (4u)
|
||||
#define IOF_SPI1_DQ2 (6u)
|
||||
#define IOF_SPI1_DQ3 (7u)
|
||||
|
||||
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
|
||||
#define SPI2_NUM_SS (1)
|
||||
#define IOF_SPI2_SS0 (26u)
|
||||
#define IOF_SPI2_MOSI (27u)
|
||||
#define IOF_SPI2_MISO (28u)
|
||||
#define IOF_SPI2_SCK (29u)
|
||||
#define IOF_SPI2_DQ0 (27u)
|
||||
#define IOF_SPI2_DQ1 (28u)
|
||||
#define IOF_SPI2_DQ2 (30u)
|
||||
#define IOF_SPI2_DQ3 (31u)
|
||||
|
||||
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
|
||||
|
||||
#define IOF0_UART0_MASK _AC(0x00030000, UL)
|
||||
#define IOF_UART0_RX (16u)
|
||||
#define IOF_UART0_TX (17u)
|
||||
|
||||
#define IOF0_UART1_MASK _AC(0x03000000, UL)
|
||||
#define IOF_UART1_RX (24u)
|
||||
#define IOF_UART1_TX (25u)
|
||||
|
||||
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
|
||||
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
|
||||
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
|
||||
|
||||
// Interrupt numbers
|
||||
#define INT_RESERVED 0
|
||||
#define INT_WDOGCMP 1
|
||||
#define INT_RTCCMP 2
|
||||
#define INT_UART0_BASE 3
|
||||
#define INT_UART1_BASE 4
|
||||
#define INT_SPI0_BASE 5
|
||||
#define INT_SPI1_BASE 6
|
||||
#define INT_SPI2_BASE 7
|
||||
#define INT_GPIO_BASE 8
|
||||
#define INT_PWM0_BASE 40
|
||||
#define INT_PWM1_BASE 44
|
||||
#define INT_PWM2_BASE 48
|
||||
|
||||
// Helper functions
|
||||
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
|
||||
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
|
||||
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
|
||||
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
|
||||
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
|
||||
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
|
||||
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
|
||||
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
|
||||
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
|
||||
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
|
||||
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
|
||||
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
|
||||
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
|
||||
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
|
||||
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
|
||||
|
||||
// Misc
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define NUM_GPIO 32
|
||||
|
||||
#define PLIC_NUM_INTERRUPTS 52
|
||||
#define PLIC_NUM_PRIORITIES 7
|
||||
|
||||
#include "hifive1.h"
|
||||
|
||||
unsigned long get_cpu_freq(void);
|
||||
unsigned long get_timer_freq(void);
|
||||
uint64_t get_timer_value(void);
|
||||
|
||||
#endif /* _SIFIVE_PLATFORM_H */
|
||||
|
|
@ -1,13 +1,27 @@
|
|||
// See LICENSE for license details.
|
||||
#include <sifive/smp.h>
|
||||
|
||||
/* This is defined in sifive/platform.h, but that can't be included from
|
||||
* assembly. */
|
||||
#define CLINT_CTRL_ADDR 0x02000000
|
||||
|
||||
.section .init
|
||||
.globl _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
la gp, _gp
|
||||
.cfi_startproc
|
||||
.cfi_undefined ra
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
la sp, _sp
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_pause(t0, t1)
|
||||
#endif
|
||||
|
||||
/* Load data section */
|
||||
la a0, _data_lma
|
||||
la a1, _data
|
||||
|
|
@ -47,8 +61,51 @@ _start:
|
|||
1:
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
smp_resume(t0, t1)
|
||||
|
||||
csrr a0, mhartid
|
||||
bnez a0, 2f
|
||||
#endif
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
/* argc = argv = 0 */
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
call main
|
||||
tail exit
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#if defined(ENABLE_SMP)
|
||||
2:
|
||||
la t0, trap_entry
|
||||
csrw mtvec, t0
|
||||
|
||||
csrr a0, mhartid
|
||||
la t1, _sp
|
||||
slli t0, a0, 10
|
||||
sub sp, t1, t0
|
||||
|
||||
auipc ra, 0
|
||||
addi sp, sp, -16
|
||||
#if __riscv_xlen == 32
|
||||
sw ra, 8(sp)
|
||||
#else
|
||||
sd ra, 8(sp)
|
||||
#endif
|
||||
|
||||
call secondary_main
|
||||
tail exit
|
||||
|
||||
1:
|
||||
j 1b
|
||||
#endif
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,288 @@
|
|||
// See LICENSE for license details
|
||||
|
||||
#ifndef VENTRY_S
|
||||
#define VENTRY_S
|
||||
|
||||
#include "encoding.h"
|
||||
#include "sifive/bits.h"
|
||||
|
||||
#only save caller registers
|
||||
.macro TRAP_ENTRY
|
||||
addi sp, sp, -16*REGBYTES
|
||||
|
||||
STORE x1, 0*REGBYTES(sp)
|
||||
STORE x5, 1*REGBYTES(sp)
|
||||
STORE x6, 2*REGBYTES(sp)
|
||||
STORE x7, 3*REGBYTES(sp)
|
||||
STORE x10, 4*REGBYTES(sp)
|
||||
STORE x11, 5*REGBYTES(sp)
|
||||
STORE x12, 6*REGBYTES(sp)
|
||||
STORE x13, 7*REGBYTES(sp)
|
||||
STORE x14, 8*REGBYTES(sp)
|
||||
STORE x15, 9*REGBYTES(sp)
|
||||
STORE x16, 10*REGBYTES(sp)
|
||||
STORE x17, 11*REGBYTES(sp)
|
||||
STORE x28, 12*REGBYTES(sp)
|
||||
STORE x29, 13*REGBYTES(sp)
|
||||
STORE x30, 14*REGBYTES(sp)
|
||||
STORE x31, 15*REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
#restore caller registers
|
||||
.macro TRAP_EXIT
|
||||
# Remain in M-mode after mret
|
||||
li t0, MSTATUS_MPP
|
||||
csrs mstatus, t0
|
||||
|
||||
LOAD x1, 0*REGBYTES(sp)
|
||||
LOAD x5, 1*REGBYTES(sp)
|
||||
LOAD x6, 2*REGBYTES(sp)
|
||||
LOAD x7, 3*REGBYTES(sp)
|
||||
LOAD x10, 4*REGBYTES(sp)
|
||||
LOAD x11, 5*REGBYTES(sp)
|
||||
LOAD x12, 6*REGBYTES(sp)
|
||||
LOAD x13, 7*REGBYTES(sp)
|
||||
LOAD x14, 8*REGBYTES(sp)
|
||||
LOAD x15, 9*REGBYTES(sp)
|
||||
LOAD x16, 10*REGBYTES(sp)
|
||||
LOAD x17, 11*REGBYTES(sp)
|
||||
LOAD x28, 12*REGBYTES(sp)
|
||||
LOAD x29, 13*REGBYTES(sp)
|
||||
LOAD x30, 14*REGBYTES(sp)
|
||||
LOAD x31, 15*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 16*REGBYTES
|
||||
mret
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
#Vector table for E31/E51
|
||||
|
||||
.section .text.entry
|
||||
.align 8
|
||||
.global vtrap_entry
|
||||
vtrap_entry:
|
||||
j sync_trap
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmsi_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmti_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vmei_Handler
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j reserved
|
||||
.align 2
|
||||
j vlip_Handler0
|
||||
.align 2
|
||||
j vlip_Handler1
|
||||
.align 2
|
||||
j vlip_Handler2
|
||||
.align 2
|
||||
j vlip_Handler3
|
||||
.align 2
|
||||
j vlip_Handler4
|
||||
.align 2
|
||||
j vlip_Handler5
|
||||
.align 2
|
||||
j vlip_Handler6
|
||||
.align 2
|
||||
j vlip_Handler7
|
||||
.align 2
|
||||
j vlip_Handler8
|
||||
.align 2
|
||||
j vlip_Handler9
|
||||
.align 2
|
||||
j vlip_Handler10
|
||||
.align 2
|
||||
j vlip_Handler11
|
||||
.align 2
|
||||
j vlip_Handler12
|
||||
.align 2
|
||||
j vlip_Handler13
|
||||
.align 2
|
||||
j vlip_Handler14
|
||||
.align 2
|
||||
j vlip_Handler15
|
||||
|
||||
#synchronous trap
|
||||
sync_trap:
|
||||
TRAP_ENTRY
|
||||
jal handle_sync_trap
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine Software Interrupt
|
||||
vmsi_Handler:
|
||||
TRAP_ENTRY
|
||||
jal reserved
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine Timer Interrupt
|
||||
vmti_Handler:
|
||||
TRAP_ENTRY
|
||||
jal handle_m_time_interrupt
|
||||
TRAP_EXIT
|
||||
|
||||
#Machine External Interrupt
|
||||
vmei_Handler:
|
||||
TRAP_ENTRY
|
||||
jal handle_m_external_interrupt
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP0
|
||||
vlip_Handler0:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt0
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP1
|
||||
vlip_Handler1:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt1
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP2
|
||||
vlip_Handler2:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt2
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP3
|
||||
vlip_Handler3:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt3
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP4
|
||||
vlip_Handler4:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt4
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP5
|
||||
vlip_Handler5:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt5
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP6
|
||||
vlip_Handler6:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt6
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP7
|
||||
vlip_Handler7:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt7
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP8
|
||||
vlip_Handler8:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt8
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP9
|
||||
vlip_Handler9:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt9
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP10
|
||||
vlip_Handler10:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt10
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP11
|
||||
vlip_Handler11:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt11
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP12
|
||||
vlip_Handler12:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt12
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP13
|
||||
vlip_Handler13:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt13
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP14
|
||||
vlip_Handler14:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt14
|
||||
TRAP_EXIT
|
||||
|
||||
#LIP15
|
||||
vlip_Handler15:
|
||||
TRAP_ENTRY
|
||||
jal handle_local_interrupt15
|
||||
TRAP_EXIT
|
||||
|
||||
#unimplemented ISRs trap here
|
||||
.weak reserved
|
||||
reserved:
|
||||
.weak handle_local_interrupt0
|
||||
handle_local_interrupt0:
|
||||
.weak handle_local_interrupt1
|
||||
handle_local_interrupt1:
|
||||
.weak handle_local_interrupt2
|
||||
handle_local_interrupt2:
|
||||
.weak handle_local_interrupt3
|
||||
handle_local_interrupt3:
|
||||
.weak handle_local_interrupt4
|
||||
handle_local_interrupt4:
|
||||
.weak handle_local_interrupt5
|
||||
handle_local_interrupt5:
|
||||
.weak handle_local_interrupt6
|
||||
handle_local_interrupt6:
|
||||
.weak handle_local_interrupt7
|
||||
handle_local_interrupt7:
|
||||
.weak handle_local_interrupt8
|
||||
handle_local_interrupt8:
|
||||
.weak handle_local_interrupt9
|
||||
handle_local_interrupt9:
|
||||
.weak handle_local_interrupt10
|
||||
handle_local_interrupt10:
|
||||
.weak handle_local_interrupt11
|
||||
handle_local_interrupt11:
|
||||
.weak handle_local_interrupt12
|
||||
handle_local_interrupt12:
|
||||
.weak handle_local_interrupt13
|
||||
handle_local_interrupt13:
|
||||
.weak handle_local_interrupt14
|
||||
handle_local_interrupt14:
|
||||
.weak handle_local_interrupt15
|
||||
handle_local_interrupt15:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
#endif
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _RISCV_BITS_H
|
||||
#define _RISCV_BITS_H
|
||||
|
||||
|
|
@ -17,7 +18,7 @@
|
|||
#define STR(x) XSTR(x)
|
||||
#define XSTR(x) #x
|
||||
|
||||
#ifdef __riscv64
|
||||
#if __riscv_xlen == 64
|
||||
# define SLL32 sllw
|
||||
# define STORE sd
|
||||
# define LOAD ld
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// See LICENSE for license details.
|
||||
/* Derived from <linux/const.h> */
|
||||
|
||||
#ifndef _SIFIVE_CONST_H
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_CLIC_H
|
||||
#define _SIFIVE_CLIC_H
|
||||
|
||||
#define CLIC_HART0 0x00800000
|
||||
#define CLIC_MSIP 0x0000
|
||||
#define CLIC_MSIP_size 0x4
|
||||
#define CLIC_MTIMECMP 0x4000
|
||||
#define CLIC_MTIMECMP_size 0x8
|
||||
#define CLIC_MTIME 0xBFF8
|
||||
#define CLIC_MTIME_size 0x8
|
||||
|
||||
#define CLIC_INTIP 0x000
|
||||
#define CLIC_INTIE 0x400
|
||||
#define CLIC_INTCFG 0x800
|
||||
#define CLIC_CFG 0xc00
|
||||
|
||||
// These interrupt IDs are consistent across old and new mtvec modes
|
||||
#define SSIPID 1
|
||||
#define MSIPID 3
|
||||
#define STIPID 5
|
||||
#define MTIPID 7
|
||||
#define SEIPID 9
|
||||
#define MEIPID 11
|
||||
#define CSIPID 12
|
||||
#define LOCALINTIDBASE 16
|
||||
|
||||
|
||||
#endif /* _SIFIVE_CLIC_H */
|
||||
|
|
@ -30,8 +30,8 @@
|
|||
|
||||
/* Fields */
|
||||
|
||||
#define SPI_SCK_POL 0x1
|
||||
#define SPI_SCK_PHA 0x2
|
||||
#define SPI_SCK_PHA 0x1
|
||||
#define SPI_SCK_POL 0x2
|
||||
|
||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 42f
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif
|
||||
|
|
@ -26,6 +26,7 @@ LIBWRAP_SRCS := \
|
|||
sys/times.c \
|
||||
sys/sbrk.c \
|
||||
sys/_exit.c \
|
||||
sys/puts.c \
|
||||
misc/write_hex.c
|
||||
|
||||
LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f))
|
||||
|
|
@ -34,13 +35,14 @@ LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o)
|
|||
LIBWRAP_SYMS := malloc free \
|
||||
open lseek read write fstat stat close link unlink \
|
||||
execve fork getpid kill wait \
|
||||
isatty times sbrk _exit
|
||||
isatty times sbrk _exit puts
|
||||
|
||||
LIBWRAP := libwrap.a
|
||||
|
||||
LINK_DEPS += $(LIBWRAP)
|
||||
|
||||
LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s))
|
||||
LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=_$(s))
|
||||
LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group
|
||||
|
||||
CLEAN_OBJS += $(LIBWRAP_OBJS)
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
#include <unistd.h>
|
||||
#include "platform.h"
|
||||
|
||||
void write_hex(int fd, uint32_t hex)
|
||||
void write_hex(int fd, unsigned long int hex)
|
||||
{
|
||||
uint8_t ii;
|
||||
uint8_t jj;
|
||||
char towrite;
|
||||
write(fd , "0x", 2);
|
||||
for (ii = 8 ; ii > 0; ii--) {
|
||||
for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {
|
||||
jj = ii - 1;
|
||||
uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
|
||||
towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
|
||||
|
|
|
|||
|
|
@ -2,12 +2,11 @@
|
|||
|
||||
#include <unistd.h>
|
||||
#include "platform.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
void __wrap__exit(int code)
|
||||
void __wrap_exit(int code)
|
||||
{
|
||||
//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
|
||||
const char message[] = "\nProgam has exited with code:";
|
||||
//*leds = (~(code));
|
||||
|
||||
write(STDERR_FILENO, message, sizeof(message) - 1);
|
||||
write_hex(STDERR_FILENO, code);
|
||||
|
|
@ -15,3 +14,4 @@ void __wrap__exit(int code)
|
|||
|
||||
for (;;);
|
||||
}
|
||||
weak_under_alias(exit);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_close(int fd)
|
||||
{
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(close);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_execve(const char* name, char* const argv[], char* const env[])
|
||||
{
|
||||
return _stub(ENOMEM);
|
||||
}
|
||||
weak_under_alias(execve);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <unistd.h>
|
||||
#include <sys/stat.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_fstat(int fd, struct stat* st)
|
||||
{
|
||||
|
|
@ -14,3 +15,4 @@ int __wrap_fstat(int fd, struct stat* st)
|
|||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(fstat);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/* See LICENSE of license details. */
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
weak_under_alias(getpid);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <unistd.h>
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_isatty(int fd)
|
||||
{
|
||||
|
|
@ -9,3 +10,4 @@ int __wrap_isatty(int fd)
|
|||
|
||||
return 0;
|
||||
}
|
||||
weak_under_alias(isatty);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_kill(int pid, int sig)
|
||||
{
|
||||
return _stub(EINVAL);
|
||||
}
|
||||
weak_under_alias(kill);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_link(const char *old_name, const char *new_name)
|
||||
{
|
||||
return _stub(EMLINK);
|
||||
}
|
||||
weak_under_alias(link);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
off_t __wrap_lseek(int fd, off_t ptr, int dir)
|
||||
{
|
||||
|
|
@ -12,3 +13,4 @@ off_t __wrap_lseek(int fd, off_t ptr, int dir)
|
|||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(lseek);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_open(const char* name, int flags, int mode)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(open);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_openat(int dirfd, const char* name, int flags, int mode)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(openat);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_puts(const char *s)
|
||||
{
|
||||
while (*s != '\0') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = *s;
|
||||
|
||||
if (*s == '\n') {
|
||||
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
|
||||
UART0_REG(UART_REG_TXFIFO) = '\r';
|
||||
}
|
||||
|
||||
++s;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
weak_under_alias(puts);
|
||||
|
|
@ -7,12 +7,13 @@
|
|||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
ssize_t __wrap_read(int fd, void* ptr, size_t len)
|
||||
{
|
||||
uint8_t * current = (uint8_t *)ptr;
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
|
||||
volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
|
||||
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
|
||||
|
||||
ssize_t result = 0;
|
||||
|
||||
|
|
@ -28,3 +29,4 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len)
|
|||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(read);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* See LICENSE of license details. */
|
||||
|
||||
#include <stddef.h>
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
void *__wrap_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
|
|
@ -14,3 +15,4 @@ void *__wrap_sbrk(ptrdiff_t incr)
|
|||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
weak_under_alias(sbrk);
|
||||
|
|
|
|||
|
|
@ -3,8 +3,10 @@
|
|||
#include <errno.h>
|
||||
#include <sys/stat.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_stat(const char* file, struct stat* st)
|
||||
{
|
||||
return _stub(EACCES);
|
||||
}
|
||||
weak_under_alias(stat);
|
||||
|
|
|
|||
|
|
@ -3,8 +3,10 @@
|
|||
#include <errno.h>
|
||||
#include <sys/times.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
clock_t __wrap_times(struct tms* buf)
|
||||
{
|
||||
return _stub(EACCES);
|
||||
}
|
||||
weak_under_alias(times);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,10 @@
|
|||
|
||||
#include <errno.h>
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
int __wrap_unlink(const char* name)
|
||||
{
|
||||
return _stub(ENOENT);
|
||||
}
|
||||
weak_under_alias(unlink);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
|
||||
#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
|
||||
|
||||
#define weak_under_alias(name) \
|
||||
extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))
|
||||
|
||||
#endif
|
||||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include "platform.h"
|
||||
#include "stub.h"
|
||||
#include "weak_under_alias.h"
|
||||
|
||||
ssize_t __wrap_write(int fd, const void* ptr, size_t len)
|
||||
{
|
||||
|
|
@ -27,3 +28,4 @@ ssize_t __wrap_write(int fd, const void* ptr, size_t len)
|
|||
|
||||
return _stub(EBADF);
|
||||
}
|
||||
weak_under_alias(write);
|
||||
|
|
|
|||
|
|
@ -17,16 +17,8 @@ int factorial(int i){
|
|||
|
||||
int main()
|
||||
{
|
||||
FILE * out = fdopen(STDOUT_FILENO, "w");
|
||||
int value=0;
|
||||
int res = read(STDIN_FILENO, &value, 1);
|
||||
// FILE * inp = fdopen(STDIN_FILENO, "r");
|
||||
//fprintf(out, "hello world!\n");
|
||||
// int value = 0;
|
||||
// int res = fscanf(inp, "%d", value);
|
||||
// int res = scanf("%d", value);
|
||||
volatile int result = factorial (10);
|
||||
fprintf(out, "Factorial is %d\n", result);
|
||||
printf("Factorial is %d\n", result);
|
||||
printf("End of execution");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue