add second XSPN partition
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							| @@ -12,7 +12,8 @@ typedef void (*function_ptr_t) (void); | |||||||
| //! Instance data for the PLIC. | //! Instance data for the PLIC. | ||||||
| plic_instance_t g_plic; | plic_instance_t g_plic; | ||||||
| std::array<function_ptr_t,PLIC_NUM_INTERRUPTS>  g_ext_interrupt_handlers; | std::array<function_ptr_t,PLIC_NUM_INTERRUPTS>  g_ext_interrupt_handlers; | ||||||
| bool hw_interrupt{true}; | bool spn1_hw_interrupt{true}; | ||||||
|  | bool spn2_hw_interrupt{true}; | ||||||
|  |  | ||||||
|  |  | ||||||
| /*! \brief external interrupt handler | /*! \brief external interrupt handler | ||||||
| @@ -43,19 +44,26 @@ void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) | |||||||
|     PLIC_enable_interrupt(&g_plic, irq_num); |     PLIC_enable_interrupt(&g_plic, irq_num); | ||||||
| } | } | ||||||
|  |  | ||||||
| static void msi_interrupt_handler(){ | void wait_for_spn1_interrupt() { | ||||||
| 	hw_interrupt = false; |  | ||||||
| } |  | ||||||
|  |  | ||||||
| void wait_for_interrupt() { |  | ||||||
|     // wait until HW is done |     // wait until HW is done | ||||||
|     if(hw_interrupt) { |     if(spn1_hw_interrupt) { | ||||||
|         do{ |         do{ | ||||||
|             asm("wfi"); |             asm("wfi"); | ||||||
|             asm("nop"); |             asm("nop"); | ||||||
|         }while(hw_interrupt); |         }while(spn1_hw_interrupt); | ||||||
|     } |     } | ||||||
| 	hw_interrupt=true; | 	spn1_hw_interrupt=true; | ||||||
|  | } | ||||||
|  |  | ||||||
|  | void wait_for_spn2_interrupt() { | ||||||
|  |     // wait until HW is done | ||||||
|  |     if(spn2_hw_interrupt) { | ||||||
|  |         do{ | ||||||
|  |             asm("wfi"); | ||||||
|  |             asm("nop"); | ||||||
|  |         }while(spn2_hw_interrupt); | ||||||
|  |     } | ||||||
|  |     spn2_hw_interrupt=true; | ||||||
| } | } | ||||||
|  |  | ||||||
| /*!\brief initializes platform | /*!\brief initializes platform | ||||||
| @@ -77,7 +85,6 @@ void platform_init(){ | |||||||
|     clear_csr(mie, MIP_MEIP); |     clear_csr(mie, MIP_MEIP); | ||||||
|     clear_csr(mie, MIP_MTIP); |     clear_csr(mie, MIP_MTIP); | ||||||
|     for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler; |     for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler; | ||||||
|     configure_irq(2, msi_interrupt_handler); |  | ||||||
|     // Enable interrupts in general. |     // Enable interrupts in general. | ||||||
|     set_csr(mstatus, MSTATUS_MIE); |     set_csr(mstatus, MSTATUS_MIE); | ||||||
|     // Enable the Machine-External bit in MIE |     // Enable the Machine-External bit in MIE | ||||||
|   | |||||||
| @@ -3,21 +3,41 @@ | |||||||
| #include "init.h" | #include "init.h" | ||||||
| #include "spn_checker_regs.h" | #include "spn_checker_regs.h" | ||||||
|  |  | ||||||
| using spn = spn_regs<0x90000000>; | using spn_1 = spn_regs<0x90000000>; | ||||||
|  | using spn_2 = spn_regs<0xC0000000>; | ||||||
| using spn_checker = spn_checker_regs<0x10040000>; | using spn_checker = spn_checker_regs<0x10040000>; | ||||||
|  |  | ||||||
| void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) { | void run_xspn1(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) { | ||||||
|     spn::mode_reg() = 0; |     printf("Starting first XSPN instance\n"); | ||||||
|     spn::input_length_reg() = num_samples;      // each sample consists of 5 uint8 values |     spn_1::mode_reg() = 0; | ||||||
|     spn::input_addr_reg() = in_addr; |     spn_1::input_length_reg() = num_samples;      // each sample consists of 5 uint8 values | ||||||
|     spn::output_addr_reg() = out_addr; |     spn_1::input_addr_reg() = in_addr; | ||||||
|     spn::num_of_in_beats_reg() = in_beats;  // Number of AXI4 burst beats needed to load all input data |     spn_1::output_addr_reg() = out_addr; | ||||||
|     spn::num_of_out_beats_reg() = out_beats;    // Number of AXI4 burst beats needed to store all result data |     spn_1::num_of_in_beats_reg() = in_beats;  // Number of AXI4 burst beats needed to load all input data | ||||||
|     printf("Starting XSPN\n"); |     spn_1::num_of_out_beats_reg() = out_beats;    // Number of AXI4 burst beats needed to store all result data | ||||||
|     spn::start_reg() = 1; |     spn_1::start_reg() = 1; | ||||||
| } | } | ||||||
|  |  | ||||||
|  | void run_xspn2(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) { | ||||||
|  |     printf("Starting second XSPN instance\n"); | ||||||
|  |     spn_2::mode_reg() = 0; | ||||||
|  |     spn_2::input_length_reg() = num_samples;      // each sample consists of 5 uint8 values | ||||||
|  |     spn_2::input_addr_reg() = in_addr; | ||||||
|  |     spn_2::output_addr_reg() = out_addr; | ||||||
|  |     spn_2::num_of_in_beats_reg() = in_beats;  // Number of AXI4 burst beats needed to load all input data | ||||||
|  |     spn_2::num_of_out_beats_reg() = out_beats;    // Number of AXI4 burst beats needed to store all result data | ||||||
|  |     spn_2::start_reg() = 1; | ||||||
|  | } | ||||||
|  |  | ||||||
|  | static void spn1_interrupt_handler(){ | ||||||
|  | 	spn1_hw_interrupt = false; | ||||||
|  |     spn_1::interrupt_reg() = 1; | ||||||
|  | } | ||||||
|  |  | ||||||
|  | static void spn2_interrupt_handler(){ | ||||||
|  | 	spn2_hw_interrupt = false; | ||||||
|  |     spn_2::interrupt_reg() = 1; | ||||||
|  | } | ||||||
| /*! \brief main function | /*! \brief main function | ||||||
|  * |  * | ||||||
|  */ |  */ | ||||||
| @@ -25,13 +45,20 @@ int main() { | |||||||
|  |  | ||||||
|  |  | ||||||
|     platform_init(); |     platform_init(); | ||||||
|  |     configure_irq(2, spn1_interrupt_handler); | ||||||
|  |     configure_irq(22, spn2_interrupt_handler); | ||||||
|  |  | ||||||
|     spn::mode_reg() = 1; |     spn_1::mode_reg() = 1; | ||||||
|     spn::start_reg() = 1; |     spn_1::start_reg() = 1; | ||||||
|     wait_for_interrupt(); |     wait_for_spn1_interrupt(); | ||||||
|     spn::interrupt_reg() = 1; |     uint32_t readout = spn_1::readout_reg(); | ||||||
|     uint32_t readout = spn::readout_reg(); |     printf("READOUT first HW instance:0x%x\n", readout); | ||||||
|     printf("READOUT HW:0x%x\n", readout); |  | ||||||
|  |     spn_2::mode_reg() = 1; | ||||||
|  |     spn_2::start_reg() = 1; | ||||||
|  |     wait_for_spn2_interrupt(); | ||||||
|  |     uint32_t readout2 = spn_2::readout_reg(); | ||||||
|  |     printf("READOUT second HW instance:0x%x\n", readout2); | ||||||
|  |  | ||||||
|     uint32_t axi_bytes = readout; |     uint32_t axi_bytes = readout; | ||||||
|     axi_bytes = axi_bytes & 0xff; |     axi_bytes = axi_bytes & 0xff; | ||||||
| @@ -42,24 +69,23 @@ int main() { | |||||||
|     uint32_t sample_bytes = readout; |     uint32_t sample_bytes = readout; | ||||||
|     sample_bytes = sample_bytes >> 16; |     sample_bytes = sample_bytes >> 16; | ||||||
|     sample_bytes = sample_bytes / 8; |     sample_bytes = sample_bytes / 8; | ||||||
|  |  | ||||||
|     printf("Sample Bytes: %d\n", sample_bytes); |     printf("Sample Bytes: %d\n", sample_bytes); | ||||||
|  |  | ||||||
|     uint32_t result_bytes = 8; |     uint32_t result_bytes = 8; | ||||||
|  |  | ||||||
|     printf("Result Bytes: %d\n", result_bytes); |     printf("Result Bytes: %d\n", result_bytes); | ||||||
|  |  | ||||||
|     const uint32_t amount_of_input_samples = 50000; |     const uint32_t amount_of_input_samples = 50000; | ||||||
|     uint32_t step = 50000; |     uint32_t step = 50000; | ||||||
|     uint32_t iterations = 15; |     uint32_t iterations = 5; | ||||||
|      |      | ||||||
|     uint32_t in_beats = (step * sample_bytes) / axi_bytes; |     uint32_t in_beats = (step * sample_bytes) / axi_bytes; | ||||||
|     if (in_beats * axi_bytes < step * sample_bytes) in_beats++; |     if (in_beats * axi_bytes < step * sample_bytes) in_beats++; | ||||||
|     uint32_t out_beats = (step * result_bytes) / axi_bytes; |     uint32_t out_beats = (step * result_bytes) / axi_bytes; | ||||||
|     if (out_beats * axi_bytes < step * result_bytes) out_beats++; |     if (out_beats * axi_bytes < step * result_bytes) out_beats++; | ||||||
|  |  | ||||||
|     int in_addr  = 0x20010000; // place input samples in the SPI memory |     int in_addr   = 0x20010000; // place input samples in the SPI memory | ||||||
|     int out_addr = 0x20510000; |     int out_addr1 = 0x20510000; | ||||||
|  |     int out_addr2 = 0x20520000; | ||||||
|  |  | ||||||
|     // inject SPN input data |     // inject SPN input data | ||||||
|     spn_checker::input_addr_reg() = in_addr; |     spn_checker::input_addr_reg() = in_addr; | ||||||
| @@ -67,17 +93,17 @@ int main() { | |||||||
|     spn_checker::start_data_trans_reg() = 1; |     spn_checker::start_data_trans_reg() = 1; | ||||||
|  |  | ||||||
|  |  | ||||||
|     spn_checker::output_addr_reg() = out_addr; |     spn_checker::output_addr_reg() = out_addr1; | ||||||
|     for (int k = 0; k < iterations*step; k+=step) { |     for (int k = 0; k < iterations*step; k+=step) { | ||||||
|         run_xspn(in_addr, out_addr, step, in_beats, out_beats); |         run_xspn1(in_addr, out_addr1, step, in_beats, out_beats); | ||||||
|         wait_for_interrupt(); |         run_xspn2(in_addr, out_addr2, step, in_beats, out_beats); | ||||||
|  |         wait_for_spn1_interrupt(); | ||||||
|  |         wait_for_spn2_interrupt(); | ||||||
|         printf("XSPN finished\n"); |         printf("XSPN finished\n"); | ||||||
|         spn_checker::offset_reg() = k; |         spn_checker::offset_reg() = k; | ||||||
|         spn_checker::length_reg() = step; |         spn_checker::length_reg() = step; | ||||||
|         spn_checker::start_result_check_reg() = 1; |         spn_checker::start_result_check_reg() = 1; | ||||||
|  |  | ||||||
|         spn::interrupt_reg() = 1; |  | ||||||
|  |  | ||||||
|         in_addr += step * sample_bytes; // 5 bytes in each sample |         in_addr += step * sample_bytes; // 5 bytes in each sample | ||||||
|         if (k == amount_of_input_samples) { |         if (k == amount_of_input_samples) { | ||||||
|         	in_addr = 0x20010000; |         	in_addr = 0x20010000; | ||||||
|   | |||||||
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