updates ehrenberg devices and BSP
This commit is contained in:
parent
c94eb7c61a
commit
231366cc94
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@ -4,7 +4,7 @@ _MK_COMMON := # defined
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TL_TARGET?=all
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TL_TARGET?=all
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.PHONY: $(TL_TARGET)
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.PHONY: $(TL_TARGET)
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$(TL_TARGET): $(TARGET)
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$(TL_TARGET): $(TARGET).elf
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ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
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ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
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BSP_BASE=$(ENV_DIR)/..
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BSP_BASE=$(ENV_DIR)/..
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@ -63,8 +63,7 @@ OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
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OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
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OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
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ifndef NO_DEFAULT_LINK
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ifndef NO_DEFAULT_LINK
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$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
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$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
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echo LINK_OBJS: $(LINK_OBJS)
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$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
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$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
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$(OBJDUMP) -d -S $@ > $(TARGET).dis
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$(OBJDUMP) -d -S $@ > $(TARGET).dis
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endif
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endif
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@ -0,0 +1,170 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY( _start )
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MEMORY
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{
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rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 1k
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
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}
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PHDRS
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{
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rom PT_LOAD;
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ram_init PT_LOAD;
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ram PT_NULL;
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}
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SECTIONS
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{
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__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
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.init ORIGIN(rom) :
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{
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KEEP (*(SORT_NONE(.init)))
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} >rom AT>rom :rom
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.text :
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{
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*(.text.unlikely .text.unlikely.*)
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*(.text.startup .text.startup.*)
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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} >rom AT>rom :rom
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.fini :
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{
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KEEP (*(SORT_NONE(.fini)))
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} >rom AT>rom :rom
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PROVIDE (__etext = .);
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PROVIDE (_etext = .);
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} >rom AT>rom :rom
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. = ALIGN(4);
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >rom AT>rom :rom
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >rom AT>rom :rom
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >rom AT>rom :rom
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.ctors :
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{
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/* gcc uses crtbegin.o to find the start of
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the constructors, so we make sure it is
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first. Because this is a wildcard, it
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doesn't matter if the user does not
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actually link against crtbegin.o; the
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linker won't look for a file to match a
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wildcard. The wildcard also means that it
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doesn't matter which directory crtbegin.o
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is in. */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*crtbegin?.o(.ctors))
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/* We don't want to include the .ctor section from
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the crtend.o file until after the sorted ctors.
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The .ctor section from the crtend file contains the
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end of ctors marker and it must be last */
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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} >rom AT>rom :rom
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.dtors :
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{
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KEEP (*crtbegin.o(.dtors))
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KEEP (*crtbegin?.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >rom AT>rom :rom
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.lalign :
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{
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. = ALIGN(4);
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PROVIDE( _data_lma = . );
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} >rom AT>rom :rom
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE( _data = . );
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} >ram AT>rom :ram_init
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.data :
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{
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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} >ram AT>rom :ram_init
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.srodata :
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{
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} >ram AT>rom :ram_init
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.sdata :
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{
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*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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} >ram AT>rom :ram_init
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. = ALIGN(4);
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PROVIDE( _edata = . );
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PROVIDE( edata = . );
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PROVIDE( _fbss = . );
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PROVIDE( __bss_start = . );
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.bss :
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{
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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} >ram AT>ram :ram
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. = ALIGN(8);
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PROVIDE( _end = . );
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PROVIDE( end = . );
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.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
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{
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PROVIDE( _heap_end = . );
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. = __stack_size;
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PROVIDE( _sp = . );
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} >ram AT>ram :ram
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PROVIDE( tohost = 0xfffffff0 );
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PROVIDE( fromhost = 0xfffffff8 );
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}
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@ -37,11 +37,11 @@ _start:
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2:
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2:
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/* Call global constructors */
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/* Call global constructors */
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//#ifdef HAVE_INIT_FINI
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#ifndef HAVE_NO_INIT_FINI
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la a0, __libc_fini_array
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la a0, __libc_fini_array
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call atexit
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call atexit
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call __libc_init_array
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call __libc_init_array
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//#endif
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#endif
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#ifndef __riscv_float_abi_soft
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#ifndef __riscv_float_abi_soft
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/* Enable FPU */
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/* Enable FPU */
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li t0, MSTATUS_FS
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li t0, MSTATUS_FS
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -3,7 +3,7 @@
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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* by peakrdl_mnrs version 1.2.5
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*/
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*/
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@ -32,6 +32,10 @@ typedef struct __attribute((__packed__)) {
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#define UART_RX_TX_REG_TX_FREE_MASK 0x1
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#define UART_RX_TX_REG_TX_FREE_MASK 0x1
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#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
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#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
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#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
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#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
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#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
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@ -115,6 +119,9 @@ inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
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inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
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inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 15) & 0x1;
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return (reg->RX_TX_REG >> 15) & 0x1;
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}
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}
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inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 16) & 0x1;
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}
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//UART_INT_CTRL_REG
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//UART_INT_CTRL_REG
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inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
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inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
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@ -4,7 +4,7 @@
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#include <stdint.h>
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#include <stdint.h>
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#include "gen/gpio.h"
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#include "gen/gpio.h"
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inline void gpio_init(gpio_t* reg) {
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inline void gpio_init(volatile gpio_t* reg) {
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set_gpio_write(reg, 0);
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set_gpio_write(reg, 0);
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set_gpio_writeEnable(reg, 0);
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set_gpio_writeEnable(reg, 0);
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}
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}
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@ -4,20 +4,24 @@
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#include <stdint.h>
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#include <stdint.h>
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#include "gen/uart.h"
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#include "gen/uart.h"
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static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
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static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
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return (reg->STATUS_REG >> 16) & 0xFF;
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return get_uart_rx_tx_reg_tx_free(reg);
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}
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}
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static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
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static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
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return reg->STATUS_REG >> 24;
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return get_uart_rx_tx_reg_tx_empty(reg);
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}
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}
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static inline void uart_write(volatile uart_t *reg, uint8_t data){
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static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
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return get_uart_rx_tx_reg_rx_avail(reg);
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}
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static inline void uart_write(volatile uart_t* reg, uint8_t data){
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while(get_uart_rx_tx_reg_tx_free(reg) == 0);
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while(get_uart_rx_tx_reg_tx_free(reg) == 0);
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set_uart_rx_tx_reg_data(reg, data);
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set_uart_rx_tx_reg_data(reg, data);
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}
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}
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static inline inline uint8_t uart_read(volatile uart_t *reg){
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static inline inline uint8_t uart_read(volatile uart_t* reg){
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uint32_t res = get_uart_rx_tx_reg_data(reg);
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uint32_t res = get_uart_rx_tx_reg_data(reg);
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||||||
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
|
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
|
||||||
return res;
|
return res;
|
||||||
|
|
Loading…
Reference in New Issue