Firmware/MNRS-BM-BSP
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updates ehrenberg devices and BSP

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This commit is contained in:
Eyck Jentzsch
2024-06-10 10:13:07 +02:00
parent c94eb7c61a
commit 231366cc94
13 changed files with 200 additions and 20 deletions
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2
include/ehrenberg/devices/gen/aclint.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/apb3spi.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/camera.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/gpio.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/i2s.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/simpledma.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

2
include/ehrenberg/devices/gen/timercounter.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/

9
include/ehrenberg/devices/gen/uart.h
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@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-05-30 18:25:57 UTC
* Generated at 2024-06-08 13:20:02 UTC
* by peakrdl_mnrs version 1.2.5
*/
@ -32,6 +32,10 @@ typedef struct __attribute((__packed__)) {
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
@ -115,6 +119,9 @@ inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
}
//UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){