Firmware/MNRS-BM-BSP
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updates sysctrl register declarations

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This commit is contained in:
Eyck Jentzsch 2025-02-19 17:17:04 +01:00
parent c37b7243b4
commit 2231ae4106
1 changed files with 19 additions and 9 deletions
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28
include/ehrenberg/devices/gen/sysctrl.h
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@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2025-02-18 11:11:47 UTC * Generated at 2025-02-19 17:15:41 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
@ -18,11 +18,15 @@ typedef struct {
volatile uint32_t AXI_BACKUP; volatile uint32_t AXI_BACKUP;
}sysctrl_t; }sysctrl_t;
#define SYSCTRL_SYSCTRL_CC_RESET_OFFS 0 #define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
#define SYSCTRL_SYSCTRL_CC_RESET_MASK 0x3 #define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
#define SYSCTRL_SYSCTRL_CC_RESET(V) ((V & SYSCTRL_SYSCTRL_CC_RESET_MASK) << SYSCTRL_SYSCTRL_CC_RESET_OFFS) #define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 2 #define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
#define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1 #define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
#define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS) #define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
@ -53,17 +57,23 @@ inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){ inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
reg->SYSCTRL = value; reg->SYSCTRL = value;
} }
inline uint32_t get_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg){ inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 0) & 0x3; return (reg->SYSCTRL >> 0) & 0x3;
} }
inline void set_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg, uint8_t value){ inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0); reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 2) & 0x3;
}
inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
}
inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){ inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 2) & 0x1; return (reg->SYSCTRL >> 4) & 0x1;
} }
inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){ inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 2)) | (value << 2); reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
} }
//SYSCTRL_PLLCTRL //SYSCTRL_PLLCTRL