wait for interrupt instead of time delay
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							| @@ -0,0 +1,85 @@ | ||||
| #ifndef SRC_INIT_H_ | ||||
| #define SRC_INIT_H_ | ||||
|  | ||||
| #include <cstdio> | ||||
| #include <array> | ||||
|  | ||||
| #include "delay.h" | ||||
| #include "bsp.h" | ||||
| #include "plic/plic_driver.h" | ||||
|  | ||||
| typedef void (*function_ptr_t) (void); | ||||
| //! Instance data for the PLIC. | ||||
| plic_instance_t g_plic; | ||||
| std::array<function_ptr_t,PLIC_NUM_INTERRUPTS>  g_ext_interrupt_handlers; | ||||
| bool hw_interrupt{false}; | ||||
|  | ||||
|  | ||||
| /*! \brief external interrupt handler | ||||
|  * | ||||
|  * routes the peripheral interrupts to the the respective handler | ||||
|  * | ||||
|  */ | ||||
| extern "C" void handle_m_ext_interrupt() { | ||||
|     plic_source int_num  = PLIC_claim_interrupt(&g_plic); | ||||
|     if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) | ||||
|       g_ext_interrupt_handlers[int_num](); | ||||
|     else | ||||
|       exit(1 + (uintptr_t) int_num); | ||||
|     PLIC_complete_interrupt(&g_plic, int_num); | ||||
| } | ||||
| /*! \brief dummy interrupt handler | ||||
|  * | ||||
|  */ | ||||
| void no_interrupt_handler (void) {}; | ||||
| /*! \brief configure the per-interrupt handler | ||||
|  * | ||||
|  */ | ||||
| void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) { | ||||
|     g_ext_interrupt_handlers[irq_num] = handler; | ||||
|     // Priority must be set > 0 to trigger the interrupt. | ||||
|     PLIC_set_priority(&g_plic, irq_num, prio); | ||||
|     // Have to enable the interrupt both at the GPIO level, and at the PLIC level. | ||||
|     PLIC_enable_interrupt(&g_plic, irq_num); | ||||
| } | ||||
|  | ||||
| static void msi_interrupt_handler(){ | ||||
| 	hw_interrupt = true; | ||||
| } | ||||
|  | ||||
| void wait_for_interrupt() { | ||||
| 	while (!hw_interrupt) { | ||||
| 		delayUS(1); | ||||
| 	}; | ||||
| 	hw_interrupt = false; | ||||
| } | ||||
|  | ||||
| /*!\brief initializes platform | ||||
|  * | ||||
|  */ | ||||
| void platform_init(){ | ||||
| 	// UART init section TODO: clarify how to get the functions from init.c? | ||||
| 	GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; | ||||
| 	GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; | ||||
| 	UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; | ||||
|  | ||||
|     F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ); | ||||
|     printf("core freq at %d Hz\n", F_CPU); | ||||
|     // initialie interupt & trap handling | ||||
|     write_csr(mtvec, &trap_entry); | ||||
|  | ||||
|     PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0); | ||||
|     // Disable the machine & timer interrupts until setup is done. | ||||
|     clear_csr(mie, MIP_MEIP); | ||||
|     clear_csr(mie, MIP_MTIP); | ||||
|     for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler; | ||||
|     configure_irq(2, msi_interrupt_handler); | ||||
|     // Enable interrupts in general. | ||||
|     set_csr(mstatus, MSTATUS_MIE); | ||||
|     // Enable the Machine-External bit in MIE | ||||
|     set_csr(mie, MIP_MEIP); | ||||
|  | ||||
| 	hw_interrupt = false; | ||||
| } | ||||
|  | ||||
| #endif /* SRC_INIT_H_ */ | ||||
| @@ -1,88 +1,16 @@ | ||||
| #include "raven_spn.h" | ||||
| #include "spn_regs.h" | ||||
| #include "delay.h" | ||||
| #include "bsp.h" | ||||
| #include "plic/plic_driver.h" | ||||
| #include "init.h" | ||||
|  | ||||
| #include <cstdio> | ||||
| #include <cstdint> | ||||
| #include <array> | ||||
| #include <cmath> | ||||
| #include <cmath> // log | ||||
|  | ||||
| using spn =spn_regs<0x90000000>; | ||||
|  | ||||
| #define IOF_ENABLE_TERMINAL (0x30000) | ||||
|  | ||||
| // huge arrays of XSPN input and referance data | ||||
| extern std::array<uint8_t, 50000> input_data; | ||||
| extern std::array<double, 10000> ref_data; | ||||
| constexpr auto ln2 = std::log(2); | ||||
|  | ||||
|  | ||||
| typedef void (*function_ptr_t) (void); | ||||
| //! Instance data for the PLIC. | ||||
| plic_instance_t g_plic; | ||||
| std::array<function_ptr_t,PLIC_NUM_INTERRUPTS>  g_ext_interrupt_handlers; | ||||
|  | ||||
|  | ||||
| /*! \brief external interrupt handler | ||||
|  * | ||||
|  * routes the peripheral interrupts to the the respective handler | ||||
|  * | ||||
|  */ | ||||
| extern "C" void handle_m_ext_interrupt() { | ||||
|     plic_source int_num  = PLIC_claim_interrupt(&g_plic); | ||||
|     if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) | ||||
|       g_ext_interrupt_handlers[int_num](); | ||||
|     else | ||||
|       exit(1 + (uintptr_t) int_num); | ||||
|     PLIC_complete_interrupt(&g_plic, int_num); | ||||
| } | ||||
| /*! \brief dummy interrupt handler | ||||
|  * | ||||
|  */ | ||||
| void no_interrupt_handler (void) {}; | ||||
| /*! \brief configure the per-interrupt handler | ||||
|  * | ||||
|  */ | ||||
| void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) { | ||||
|     g_ext_interrupt_handlers[irq_num] = handler; | ||||
|     // Priority must be set > 0 to trigger the interrupt. | ||||
|     PLIC_set_priority(&g_plic, irq_num, prio); | ||||
|     // Have to enable the interrupt both at the GPIO level, and at the PLIC level. | ||||
|     PLIC_enable_interrupt(&g_plic, irq_num); | ||||
| } | ||||
|  | ||||
| static void msi_interrupt_handler(){ | ||||
|     printf("INterrupt handler call\n"); | ||||
| } | ||||
|  | ||||
| /*!\brief initializes platform | ||||
|  * | ||||
|  */ | ||||
| void platform_init(){ | ||||
| 	// UART init section TODO: clarify how to get the functions from init.c? | ||||
| 	GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; | ||||
| 	GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; | ||||
| 	UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; | ||||
|  | ||||
|     F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ); | ||||
|     printf("core freq at %d Hz\n", F_CPU); | ||||
|     // initialie interupt & trap handling | ||||
|     write_csr(mtvec, &trap_entry); | ||||
|  | ||||
|     PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0); | ||||
|     // Disable the machine & timer interrupts until setup is done. | ||||
|     clear_csr(mie, MIP_MEIP); | ||||
|     clear_csr(mie, MIP_MTIP); | ||||
|     for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler; | ||||
|     configure_irq(2, msi_interrupt_handler); | ||||
|     // Enable interrupts in general. | ||||
|     set_csr(mstatus, MSTATUS_MIE); | ||||
|     // Enable the Machine-External bit in MIE | ||||
|     set_csr(mie, MIP_MEIP); | ||||
| } | ||||
|  | ||||
| bool double_equals(double a, double b, double epsilon = 0.001) | ||||
| { | ||||
|     return std::abs(a - b) < epsilon; | ||||
| @@ -92,11 +20,12 @@ void run_xspn() { | ||||
| 	spn::mode_reg() = 0; | ||||
| 	spn::input_length_reg() = 100; 		// each sample consists of 5 uint8 values | ||||
| 	spn::input_addr_reg() = 0x800C0000; | ||||
| 	spn::output_addr_reg() = 0x8001C000; | ||||
| 	spn::output_addr_reg() = 0x800A0000; | ||||
| 	spn::num_of_in_beats_reg() = 8;		// Number of AXI4 burst beats needed to load all input data | ||||
| 	spn::num_of_out_beats_reg() = 13;	// Number of AXI4 burst beats needed to store all result data | ||||
| 	spn::start_reg() = 1; | ||||
| 	delayUS(50); | ||||
|  | ||||
| 	wait_for_interrupt(); | ||||
| 	spn::interrupt_reg() = 1; | ||||
| } | ||||
|  | ||||
| @@ -107,8 +36,9 @@ int main() { | ||||
|     platform_init(); | ||||
|     spn::mode_reg() = 1; | ||||
|     spn::start_reg() = 1; | ||||
|     printf("READOUT HW:0x%x\n", spn::readout_reg()); | ||||
| 	wait_for_interrupt(); | ||||
|     spn::interrupt_reg() = 1; | ||||
|     printf("READOUT HW:0x%x\n", spn::readout_reg()); | ||||
|  | ||||
| 	for (int k = 0; k < 10000; k+=100) { | ||||
|         // write input samples into the memory | ||||
| @@ -126,7 +56,7 @@ int main() { | ||||
|     	run_xspn(); | ||||
|  | ||||
|     	// read calculation results from the memory | ||||
|         double * res_base = (double*) 0x8001C000; | ||||
|         double * res_base = (double*) 0x800A0000; | ||||
|  | ||||
|         for (int i = 0; i < 100; i++) { | ||||
|             if (!double_equals(res_base[i] * ln2, ref_data.at(k+i))) { | ||||
|   | ||||
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