2018-09-25 18:31:29 +02:00
|
|
|
// See LICENSE for license details
|
|
|
|
|
|
|
|
|
|
#ifndef ENTRY_S
|
|
|
|
|
#define ENTRY_S
|
|
|
|
|
|
|
|
|
|
#include "encoding.h"
|
2024-01-14 20:35:05 +01:00
|
|
|
#include "bits.h"
|
2018-09-25 18:31:29 +02:00
|
|
|
|
|
|
|
|
.section .text.entry
|
|
|
|
|
.align 2
|
|
|
|
|
.global trap_entry
|
|
|
|
|
trap_entry:
|
2023-08-20 15:00:51 +02:00
|
|
|
#ifndef __riscv_abi_rve
|
2024-01-14 08:14:57 +01:00
|
|
|
addi sp, sp, -8*REGBYTES
|
|
|
|
|
STORE x1, 1*REGBYTES(sp) // ra
|
|
|
|
|
STORE x5, 2*REGBYTES(sp) // t0
|
|
|
|
|
STORE x10, 3*REGBYTES(sp) // a0
|
|
|
|
|
STORE x11, 4*REGBYTES(sp) // a1
|
|
|
|
|
STORE x12, 5*REGBYTES(sp) // a2
|
|
|
|
|
STORE x13, 6*REGBYTES(sp) // a3
|
|
|
|
|
STORE x15, 7*REGBYTES(sp) // t1
|
|
|
|
|
#else
|
|
|
|
|
addi sp, sp, -16*REGBYTES
|
|
|
|
|
STORE x1, 1*REGBYTES(sp) // ra
|
|
|
|
|
STORE x5, 2*REGBYTES(sp) // t0
|
|
|
|
|
STORE x6, 3*REGBYTES(sp) // t1
|
|
|
|
|
STORE x7, 4*REGBYTES(sp) // t2
|
|
|
|
|
STORE x10, 5*REGBYTES(sp) // a0
|
|
|
|
|
STORE x11, 6*REGBYTES(sp) // a1
|
|
|
|
|
STORE x12, 7*REGBYTES(sp) // a2
|
|
|
|
|
STORE x13, 8*REGBYTES(sp) // a3
|
|
|
|
|
STORE x14, 9*REGBYTES(sp) // a4
|
|
|
|
|
STORE x15, 10*REGBYTES(sp) // a5
|
|
|
|
|
STORE x16, 11*REGBYTES(sp) // a6
|
|
|
|
|
STORE x17, 12*REGBYTES(sp) // a7
|
|
|
|
|
STORE x28, 13*REGBYTES(sp) // t3
|
|
|
|
|
STORE x29, 14*REGBYTES(sp) // t4
|
|
|
|
|
STORE x30, 15*REGBYTES(sp) // t5
|
|
|
|
|
STORE x31, 16*REGBYTES(sp) // t6
|
2023-08-20 15:00:51 +02:00
|
|
|
#endif
|
2018-09-25 18:31:29 +02:00
|
|
|
csrr a0, mcause
|
|
|
|
|
csrr a1, mepc
|
|
|
|
|
mv a2, sp
|
2024-02-26 20:41:15 +01:00
|
|
|
call trap
|
2018-09-25 18:31:29 +02:00
|
|
|
csrw mepc, a0
|
2023-08-20 15:00:51 +02:00
|
|
|
#ifndef __riscv_abi_rve
|
2024-01-14 08:14:57 +01:00
|
|
|
addi sp, sp, -8*REGBYTES
|
|
|
|
|
LOAD x1, 1*REGBYTES(sp) // ra
|
|
|
|
|
LOAD x5, 2*REGBYTES(sp) // t0
|
|
|
|
|
LOAD x10, 3*REGBYTES(sp) // a0
|
|
|
|
|
LOAD x11, 4*REGBYTES(sp) // a1
|
|
|
|
|
LOAD x12, 5*REGBYTES(sp) // a2
|
|
|
|
|
LOAD x13, 6*REGBYTES(sp) // a3
|
|
|
|
|
LOAD x15, 7*REGBYTES(sp) // t1
|
|
|
|
|
#else
|
|
|
|
|
addi sp, sp, -16*REGBYTES
|
|
|
|
|
LOAD x1, 1*REGBYTES(sp) // ra
|
|
|
|
|
LOAD x5, 2*REGBYTES(sp) // t0
|
|
|
|
|
LOAD x6, 3*REGBYTES(sp) // t1
|
|
|
|
|
LOAD x7, 4*REGBYTES(sp) // t2
|
|
|
|
|
LOAD x10, 5*REGBYTES(sp) // a0
|
|
|
|
|
LOAD x11, 6*REGBYTES(sp) // a1
|
|
|
|
|
LOAD x12, 7*REGBYTES(sp) // a2
|
|
|
|
|
LOAD x13, 8*REGBYTES(sp) // a3
|
|
|
|
|
LOAD x14, 9*REGBYTES(sp) // a4
|
|
|
|
|
LOAD x15, 10*REGBYTES(sp) // a5
|
|
|
|
|
LOAD x16, 11*REGBYTES(sp) // a6
|
|
|
|
|
LOAD x17, 12*REGBYTES(sp) // a7
|
|
|
|
|
LOAD x28, 13*REGBYTES(sp) // t3
|
|
|
|
|
LOAD x29, 14*REGBYTES(sp) // t4
|
|
|
|
|
LOAD x30, 15*REGBYTES(sp) // t5
|
|
|
|
|
LOAD x31, 16*REGBYTES(sp) // t6
|
2023-08-20 15:00:51 +02:00
|
|
|
#endif
|
2018-09-25 18:31:29 +02:00
|
|
|
mret
|
|
|
|
|
|
|
|
|
|
.weak handle_trap
|
|
|
|
|
handle_trap:
|
|
|
|
|
1:
|
|
|
|
|
j 1b
|
|
|
|
|
|
|
|
|
|
#endif
|
