2018-09-25 18:31:29 +02:00
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// See LICENSE for license details
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#ifndef ENTRY_S
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#define ENTRY_S
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#include "encoding.h"
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2024-01-14 20:35:05 +01:00
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#include "bits.h"
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2018-09-25 18:31:29 +02:00
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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2023-08-20 15:00:51 +02:00
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#ifndef __riscv_abi_rve
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2024-01-14 08:14:57 +01:00
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addi sp, sp, -8*REGBYTES
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STORE x1, 1*REGBYTES(sp) // ra
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STORE x5, 2*REGBYTES(sp) // t0
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STORE x10, 3*REGBYTES(sp) // a0
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STORE x11, 4*REGBYTES(sp) // a1
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STORE x12, 5*REGBYTES(sp) // a2
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STORE x13, 6*REGBYTES(sp) // a3
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STORE x15, 7*REGBYTES(sp) // t1
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#else
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addi sp, sp, -16*REGBYTES
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STORE x1, 1*REGBYTES(sp) // ra
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STORE x5, 2*REGBYTES(sp) // t0
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STORE x6, 3*REGBYTES(sp) // t1
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STORE x7, 4*REGBYTES(sp) // t2
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STORE x10, 5*REGBYTES(sp) // a0
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STORE x11, 6*REGBYTES(sp) // a1
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STORE x12, 7*REGBYTES(sp) // a2
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STORE x13, 8*REGBYTES(sp) // a3
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STORE x14, 9*REGBYTES(sp) // a4
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STORE x15, 10*REGBYTES(sp) // a5
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STORE x16, 11*REGBYTES(sp) // a6
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STORE x17, 12*REGBYTES(sp) // a7
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STORE x28, 13*REGBYTES(sp) // t3
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STORE x29, 14*REGBYTES(sp) // t4
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STORE x30, 15*REGBYTES(sp) // t5
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STORE x31, 16*REGBYTES(sp) // t6
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2023-08-20 15:00:51 +02:00
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#endif
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2018-09-25 18:31:29 +02:00
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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call handle_trap
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csrw mepc, a0
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2023-08-20 15:00:51 +02:00
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#ifndef __riscv_abi_rve
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2024-01-14 08:14:57 +01:00
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addi sp, sp, -8*REGBYTES
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LOAD x1, 1*REGBYTES(sp) // ra
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LOAD x5, 2*REGBYTES(sp) // t0
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LOAD x10, 3*REGBYTES(sp) // a0
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LOAD x11, 4*REGBYTES(sp) // a1
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LOAD x12, 5*REGBYTES(sp) // a2
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LOAD x13, 6*REGBYTES(sp) // a3
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LOAD x15, 7*REGBYTES(sp) // t1
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#else
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addi sp, sp, -16*REGBYTES
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LOAD x1, 1*REGBYTES(sp) // ra
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LOAD x5, 2*REGBYTES(sp) // t0
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LOAD x6, 3*REGBYTES(sp) // t1
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LOAD x7, 4*REGBYTES(sp) // t2
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LOAD x10, 5*REGBYTES(sp) // a0
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LOAD x11, 6*REGBYTES(sp) // a1
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LOAD x12, 7*REGBYTES(sp) // a2
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LOAD x13, 8*REGBYTES(sp) // a3
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LOAD x14, 9*REGBYTES(sp) // a4
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LOAD x15, 10*REGBYTES(sp) // a5
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LOAD x16, 11*REGBYTES(sp) // a6
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LOAD x17, 12*REGBYTES(sp) // a7
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LOAD x28, 13*REGBYTES(sp) // t3
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LOAD x29, 14*REGBYTES(sp) // t4
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LOAD x30, 15*REGBYTES(sp) // t5
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LOAD x31, 16*REGBYTES(sp) // t6
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2023-08-20 15:00:51 +02:00
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#endif
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2018-09-25 18:31:29 +02:00
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mret
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.weak handle_trap
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handle_trap:
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1:
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j 1b
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#endif
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