MNRS-BM-BSP/fpga_spn/src/raven_spn.cpp

#include "raven_spn.h"
#include "spn_regs.h"
#include "dma_regs.h"
#include "init.h"
#include "spn_checker_regs.h"

using spn = spn_regs<0x90000000>;
using dma = dma_regs<0xB0000000>;
using spn_checker = spn_checker_regs<0x10040000>;

void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_beats) {
	spn::mode_reg() = 0;
	spn::input_length_reg() = num_samples; 		// each sample consists of 5 uint8 values
	spn::input_addr_reg() = in_addr;
	spn::output_addr_reg() = out_addr;
	spn::num_of_in_beats_reg() = in_beats;	// Number of AXI4 burst beats needed to load all input data
	spn::num_of_out_beats_reg() = out_beats;	// Number of AXI4 burst beats needed to store all result data
    printf("Starting XSPN\n");
	spn::start_reg() = 1;
}

void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) {
    dma::write_reg() = direction;
    dma::fpga_address_reg() = fpga_address;
    dma::sc_address_reg() = sc_address;
    dma::bytes_reg() = num_bytes;
    dma::start_reg() = 1;
    wait_for_dma_interrupt();
    dma::clear_interrupt_reg() = 1;
}

static void spn_interrupt_handler(){
    printf("spn_interrupt_handler\n");
    hw_interrupt = false;
}

static void dma_interrupt_handler(){
    printf("dma_interrupt_handler\n");
    dma_interrupt = false;
}

/*! \brief main function
 *
 */
int main() {


    platform_init();
    configure_irq(2, spn_interrupt_handler);
    configure_irq(22, dma_interrupt_handler);

    spn::mode_reg() = 1;
    spn::start_reg() = 1;
    wait_for_spn_interrupt();
    spn::interrupt_reg() = 1;
    uint32_t readout = spn::readout_reg();
    printf("READOUT HW:0x%x\n", readout);

    uint32_t axi_bytes = readout;
    axi_bytes = axi_bytes & 0xff;
    axi_bytes = 1 << axi_bytes;

    printf("AXI Bytes: %d\n", axi_bytes);

    uint32_t sample_bytes = readout;
    sample_bytes = sample_bytes >> 16;
    sample_bytes = sample_bytes / 8;

    printf("Sample Bytes: %d\n", sample_bytes);

    uint32_t result_bytes = 8;

    printf("Result Bytes: %d\n", result_bytes);

    uint32_t step = 50000;
    uint32_t iterations = 2;

    
    uint32_t in_beats = (step * sample_bytes) / axi_bytes;
    if (in_beats * axi_bytes < step * sample_bytes) in_beats++;
    uint32_t out_beats = (step * result_bytes) / axi_bytes;
    if (out_beats * axi_bytes < step * result_bytes) out_beats++;

	int in_addr  = 0x20010000; // place input samples in the SPI memory
    int out_addr = 0x20210000;
    int fpga_address_in = 0x10000000;
    int fpga_address_out = 0x20000000;

    // inject SPN input data
    spn_checker::input_addr_reg() = in_addr;
    spn_checker::num_input_samples_reg() = sample_bytes * step * iterations;
    spn_checker::start_data_trans_reg() = 1;
    spn_checker::output_addr_reg() = out_addr;

    //run_xspn(in_addr, out_addr);
    for (int k = 0; k < iterations*step; k+=step) {
        fpga_dma(1, fpga_address_in, in_addr, step * sample_bytes);
        run_xspn(fpga_address_in, fpga_address_out, step, in_beats, out_beats);
        wait_for_spn_interrupt();
        spn::interrupt_reg() = 1;
        printf("XSPN finished\n");
        fpga_dma(0, fpga_address_out, out_addr, step * result_bytes);
        spn_checker::offset_reg() = k;
        spn_checker::length_reg() = step;
        spn_checker::start_result_check_reg() = 1;

		in_addr += step * sample_bytes; // 5 bytes in each sample
	}

	return 0;
}