Improve wait for interrupt routines
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@ -45,36 +45,34 @@ void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1)
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}
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void wait_for_spn1_interrupt() {
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clear_csr(mie, MIP_MEIP);
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// This is a time critical part. It must be ensured that no interrupt is processed between flag checking and wfi.
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// Disable interrupts and wait a few more clocks for the instruction to take effect before checking the flag.
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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while(spn1_hw_interrupt) {
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set_csr(mie, MIP_MEIP);
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asm("wfi");
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clear_csr(mie, MIP_MEIP);
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asm("nop");
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// Enable interrupts and immediately enter wfi.
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asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
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// Disable interrupts again before examine the flag value.
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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}
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spn1_hw_interrupt=true;
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set_csr(mie, MIP_MEIP);
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}
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void wait_for_spn2_interrupt() {
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clear_csr(mie, MIP_MEIP);
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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while(spn2_hw_interrupt) {
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set_csr(mie, MIP_MEIP);
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asm("wfi");
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clear_csr(mie, MIP_MEIP);
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asm("nop");
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asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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}
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spn2_hw_interrupt=true;
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set_csr(mie, MIP_MEIP);
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}
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void wait_for_spn_interrupts() {
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clear_csr(mie, MIP_MEIP);
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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while(spn1_hw_interrupt || spn2_hw_interrupt) {
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set_csr(mie, MIP_MEIP);
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asm("wfi");
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asm("nop");
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clear_csr(mie, MIP_MEIP);
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asm volatile ("csrrs x0, mie, %0; wfi; nop" : : "r"(MIP_MEIP));
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asm volatile ("csrrc x0, mie, %0; nop; nop" : : "r"(MIP_MEIP));
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}
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spn1_hw_interrupt=true;
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spn2_hw_interrupt=true;
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