Firmwares/raven_spn/src/spn_regs.h

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
//    may be used to endorse or promote products derived from this software
//    without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Oct 01 15:45:55 CEST 2020
//             *      spn_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////

#ifndef _SPN_REGS_H_
#define _SPN_REGS_H_

#include <util/bit_field.h>
#include <cstdint>

#define SPN_REG_START               0x00
#define SPN_REG_READOUT             0x10
#define SPN_REG_MODE                0x20
#define SPN_REG_INPUT_LENGTH        0x30
#define SPN_REG_INPUT_ADDR          0x40
#define SPN_REG_OUTPUT_ADDR         0x50
#define SPN_REG_NUM_OF_INPUT_BEATS  0x60
#define SPN_REG_NUM_OF_OUTPUT_BEATS 0x70
#define SPN_REG_INTERRUPT           0x0C

template<uint32_t BASE_ADDR>
class spn_regs {
public:
    // storage declarations
//    BEGIN_BF_DECL(start_t, uint32_t);
//        BF_FIELD(start, 0, 1);
//    END_BF_DECL() r_start;
    uint32_t r_start;

    uint32_t r_readout;

    uint32_t r_mode;

    uint32_t r_input_length;

    uint32_t r_input_addr;

    uint32_t r_output_addr;

    uint32_t r_num_of_input_beats;

    uint32_t r_num_of_output_beats;

//    static inline start_t& start_reg(){
//        return *reinterpret_cast<start_t*>(BASE_ADDR+SPN_REG_START);
//    }
    static inline uint32_t& start_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_START);
    }

    static inline uint32_t & readout_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_READOUT);
    }

    static inline uint32_t & mode_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_MODE);
    }

    static inline uint32_t & input_length_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INPUT_LENGTH);
    }

    static inline uint32_t & input_addr_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INPUT_ADDR);
    }

    static inline uint32_t & output_addr_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_OUTPUT_ADDR);
    }

    static inline uint32_t & num_of_in_beats_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_INPUT_BEATS);
    }

    static inline uint32_t & num_of_out_beats_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_NUM_OF_OUTPUT_BEATS);
    }

    static inline uint32_t & interrupt_reg(){
        return *reinterpret_cast<uint32_t*>(BASE_ADDR+SPN_REG_INTERRUPT);
    }

};

#endif // _SPN_REGS_H_