103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
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// See LICENSE for license details.
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#ifndef _SIFIVE_COREPLEXIP_ARTY_H
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#define _SIFIVE_COREPLEXIP_ARTY_H
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#include <stdint.h>
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/****************************************************************************
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* GPIO Connections
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*****************************************************************************/
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// These are the GPIO bit offsets for the directly driven
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// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit.
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// Additional RGB LEDs are driven by the 3 PWM outputs.
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#define RED_LED_OFFSET 0
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#define GREEN_LED_OFFSET 1
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#define BLUE_LED_OFFSET 2
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// Switch 3 is used as a GPIO input. (Switch 0 is used to set
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// the reset vector, the other switches are unused).
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#define SW_3_OFFSET 3
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// These are the buttons which are mapped as inputs.
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#define HAS_BOARD_BUTTONS
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#define BUTTON_0_OFFSET 4
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#define BUTTON_1_OFFSET 5
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#define BUTTON_2_OFFSET 6
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#define BUTTON_3_OFFSET 7
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// These are the bit offsets for the different GPIO pins
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// mapped onto the PMOD A header.
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#define JA_0_OFFSET 8
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#define JA_1_OFFSET 9
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#define JA_2_OFFSET 10
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#define JA_3_OFFSET 11
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#define JA_4_OFFSET 12
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#define JA_5_OFFSET 13
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#define JA_6_OFFSET 14
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#define JA_7_OFFSET 15
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// The below gives a mapping between global interrupt
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// sources and their number. Note that on the coreplex
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// deliverable, the io_global_interrupts go directly into
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// the PLIC. The evaluation image on the FPGA mimics a
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// system with peripheral devices which are driving the
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// global interrupt lines.
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// So, on this image, in order to get an interrupt from
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// e.g. pressing BUTTON_0:
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// 1) Steps which are external to the delivery coreplex:
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// a) The corresponding GPIO pin must be configured as in input
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// b) The "interrupt on fall" bit must be set for the GPIO pin
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// 2) Steps which would also need to be performed for the delivery coreplex:
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// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC.
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// b) The external interrupt bit must be enabled in MSTATUS
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// c) Interrupts must be enabled globally in the core.
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// Any of the above GPIO pins can be used as global interrupt
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// sources by adding their offset to the INT_GPIO_BASE.
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// For example, the buttons are shown here:
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#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET)
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#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET)
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#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET)
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#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET)
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// In addition, the Switches are mapped directly to
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// the PLIC (without going through the GPIO Peripheral).
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#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0)
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#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1)
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#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2)
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#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3)
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// This gives the mapping from inputs to LOCAL interrupts.
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#define LOCAL_INT_SW_0 0
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#define LOCAL_INT_SW_1 1
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#define LOCAL_INT_SW_2 2
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#define LOCAL_INT_SW_3 3
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#define LOCAL_INT_BTN_0 4
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#define LOCAL_INT_BTN_1 5
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#define LOCAL_INT_BTN_2 6
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#define LOCAL_INT_BTN_3 7
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#define LOCAL_INT_JA_0 8
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#define LOCAL_INT_JA_1 9
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#define LOCAL_INT_JA_2 10
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#define LOCAL_INT_JA_3 11
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#define LOCAL_INT_JA_4 12
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#define LOCAL_INT_JA_5 13
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#define LOCAL_INT_JA_6 14
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#define LOCAL_INT_JA_7 15
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#define RTC_FREQ 32768
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void write_hex(int fd, unsigned long int hex);
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#endif /* _SIFIVE_COREPLEXIP_ARTY_H */
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