fix clic_cfg access scheme

2021-11-17 07:59:02 +01:00
1 changed files with 1 additions and 1 deletions
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -1222,7 +1222,7 @@ template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
    if(addr==clic_base_addr) { // cliccfg
        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7f;
+        clic_cfg_reg&= 0x7e;
 //    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
 //        write_uint32(addr, clic_info_reg, data, length);
    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig