update generated TGC-C VM

fix JALR alignment in description
2021-09-29 00:44:17 +02:00 · 2021-09-29 00:43:42 +02:00
2 changed files with 2 additions and 2 deletions
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -517,7 +517,7 @@ private:
        // execute instruction
        try {
        {
-            int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
+            int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
            if(new_pc % traits::INSTR_ALIGNMENT) {
                raise(0,  0);
            }
Author	SHA1	Message	Date
Eyck Jentzsch	17ee7b138d	update generated TGC-C VM	2021-09-29 00:44:17 +02:00
Eyck Jentzsch	aa84a27a5b	fix JALR alignment in description	2021-09-29 00:43:42 +02:00