71 lines
1.9 KiB
Plaintext
71 lines
1.9 KiB
Plaintext
import "RV32I.core_desc"
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import "RV64I.core_desc"
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import "RVM.core_desc"
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import "RVA.core_desc"
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import "RVC.core_desc"
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import "RVF.core_desc"
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import "RVD.core_desc"
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Core MNRV32 provides RV32I/*, RV32IC */ {
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
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constants {
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XLEN:=32;
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FLEN:=64;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64I provides RV64I {
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constants {
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XLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
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constants {
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XLEN:=64;
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FLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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