944 lines
39 KiB
C++
944 lines
39 KiB
C++
/*******************************************************************************
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* Copyright (C) 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial implementation
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******************************************************************************/
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#ifndef _RISCV_HART_M_P_H
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#define _RISCV_HART_M_P_H
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#include "riscv_hart_common.h"
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#include "iss/arch/traits.h"
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#include "iss/instrumentation_if.h"
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#include "iss/log_categories.h"
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#include "iss/vm_if.h"
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <array>
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#include <elfio/elfio.hpp>
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#include <fmt/format.h>
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#include <iomanip>
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#include <sstream>
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#include <type_traits>
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#include <unordered_map>
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#include <functional>
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#include <util/bit_field.h>
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#include <util/ities.h>
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#include <util/sparse_array.h>
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#if defined(__GNUC__)
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#define likely(x) __builtin_expect(!!(x), 1)
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#define unlikely(x) __builtin_expect(!!(x), 0)
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#else
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#define likely(x) x
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#define unlikely(x) x
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#endif
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namespace iss {
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namespace arch {
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template <typename BASE> class riscv_hart_m_p : public BASE {
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protected:
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const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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const std::array<const char *, 16> trap_str = {{""
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"Instruction address misaligned", // 0
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"Instruction access fault", // 1
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"Illegal instruction", // 2
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"Breakpoint", // 3
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"Load address misaligned", // 4
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"Load access fault", // 5
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"Store/AMO address misaligned", // 6
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"Store/AMO access fault", // 7
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"Environment call from U-mode", // 8
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"Environment call from S-mode", // 9
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"Reserved", // a
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"Environment call from M-mode", // b
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"Instruction page fault", // c
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"Load page fault", // d
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"Reserved", // e
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"Store/AMO page fault"}};
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const std::array<const char *, 12> irq_str = {
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{"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
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"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
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public:
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using core = BASE;
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using this_class = riscv_hart_m_p<BASE>;
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using phys_addr_t = typename core::phys_addr_t;
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using reg_t = typename core::reg_t;
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using addr_t = typename core::addr_t;
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using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
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using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
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// primary template
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template <class T, class Enable = void> struct hart_state {};
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// specialization 32bit
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template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
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public:
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BEGIN_BF_DECL(mstatus_t, T);
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// SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
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BF_FIELD(SD, 31, 1);
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// Trap SRET
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BF_FIELD(TSR, 22, 1);
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// Timeout Wait
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BF_FIELD(TW, 21, 1);
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// Trap Virtual Memory
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BF_FIELD(TVM, 20, 1);
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// Make eXecutable Readable
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BF_FIELD(MXR, 19, 1);
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// permit Supervisor User Memory access
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BF_FIELD(SUM, 18, 1);
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// Modify PRiVilege
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BF_FIELD(MPRV, 17, 1);
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// status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
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BF_FIELD(XS, 15, 2);
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// floating-point unit status Off/Initial/Clean/Dirty
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BF_FIELD(FS, 13, 2);
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// machine previous privilege
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BF_FIELD(MPP, 11, 2);
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// supervisor previous privilege
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BF_FIELD(SPP, 8, 1);
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// previous machine interrupt-enable
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BF_FIELD(MPIE, 7, 1);
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// previous supervisor interrupt-enable
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BF_FIELD(SPIE, 5, 1);
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// previous user interrupt-enable
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BF_FIELD(UPIE, 4, 1);
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// machine interrupt-enable
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BF_FIELD(MIE, 3, 1);
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// supervisor interrupt-enable
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BF_FIELD(SIE, 1, 1);
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// user interrupt-enable
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BF_FIELD(UIE, 0, 1);
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END_BF_DECL();
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mstatus_t mstatus;
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static const reg_t mstatus_reset_val = 0x1800;
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void write_mstatus(T val) {
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auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
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auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
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mstatus = new_val;
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}
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static constexpr uint32_t get_mask() {
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//return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000 // only machine mode is supported
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// +-SD
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// | +-TSR
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// | |+-TW
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// | ||+-TVM
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// | |||+-MXR
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// | ||||+-SUM
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// | |||||+-MPRV
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// | |||||| +-XS
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// | |||||| | +-FS
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// | |||||| | | +-MPP
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// | |||||| | | | +-SPP
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// | |||||| | | | |+-MPIE
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// | ||||||/|/|/| || +-MIE
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return 0b00000000000000000001100010001000;
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}
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};
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using hart_state_type = hart_state<reg_t>;
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constexpr reg_t get_irq_mask() {
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return 0b100010001000; // only machine mode is supported
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}
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constexpr reg_t get_pc_mask() {
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return traits<BASE>::MISA_VAL&0b0100?~1:~3;
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}
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riscv_hart_m_p();
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virtual ~riscv_hart_m_p() = default;
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void reset(uint64_t address) override;
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std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
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iss::status read(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, uint8_t *const data) override;
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iss::status write(const address_type type, const access_type access, const uint32_t space,
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const uint64_t addr, const unsigned length, const uint8_t *const data) override;
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virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
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virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
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virtual uint64_t leave_trap(uint64_t flags) override;
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const reg_t& get_mhartid() const { return mhartid_reg; }
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void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
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void disass_output(uint64_t pc, const std::string instr) override {
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CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
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pc, instr, (reg_t)state.mstatus, this->reg.icount);
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};
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iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
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void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
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mem_read_cb = memReadCb;
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}
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void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
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mem_write_cb = memWriteCb;
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}
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void set_csr(unsigned addr, reg_t val){
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csr[addr & csr.page_addr_mask] = val;
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}
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if {
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riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch)
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: arch(arch) {}
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/**
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* get the name of this architecture
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*
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* @return the name of this architecture
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*/
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const std::string core_type_name() const override { return traits<BASE>::core_type; }
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virtual uint64_t get_pc() { return arch.get_pc(); };
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virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
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virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
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riscv_hart_m_p<BASE> &arch;
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};
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friend struct riscv_instrumentation_if;
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addr_t get_pc() { return this->reg.PC; }
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addr_t get_next_pc() { return this->reg.NEXT_PC; }
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virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
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virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
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virtual iss::status read_csr(unsigned addr, reg_t &val);
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virtual iss::status write_csr(unsigned addr, reg_t val);
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hart_state_type state;
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int64_t cycle_offset{0};
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uint64_t mcycle_csr{0};
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int64_t instret_offset{0};
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uint64_t minstret_csr{0};
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reg_t fault_data;
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uint64_t tohost = tohost_dflt;
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uint64_t fromhost = fromhost_dflt;
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unsigned to_host_wr_cnt = 0;
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riscv_instrumentation_if instr_if;
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using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
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using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
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using csr_page_type = typename csr_type::page_type;
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mem_type mem;
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csr_type csr;
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std::stringstream uart_buf;
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std::unordered_map<reg_t, uint64_t> ptw;
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std::unordered_map<uint64_t, uint8_t> atomic_reservation;
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std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
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std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
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private:
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iss::status read_reg(unsigned addr, reg_t &val);
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iss::status write_reg(unsigned addr, reg_t val);
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iss::status read_null(unsigned addr, reg_t &val);
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iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
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iss::status read_cycle(unsigned addr, reg_t &val);
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iss::status write_cycle(unsigned addr, reg_t val);
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iss::status read_instret(unsigned addr, reg_t &val);
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iss::status write_instret(unsigned addr, reg_t val);
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iss::status read_mtvec(unsigned addr, reg_t &val);
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iss::status read_time(unsigned addr, reg_t &val);
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iss::status read_status(unsigned addr, reg_t &val);
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iss::status write_status(unsigned addr, reg_t val);
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iss::status read_ie(unsigned addr, reg_t &val);
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iss::status write_ie(unsigned addr, reg_t val);
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iss::status read_ip(unsigned addr, reg_t &val);
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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iss::status write_mepc(unsigned addr, reg_t val);
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reg_t mhartid_reg{0x0};
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std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
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std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
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protected:
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void check_interrupt();
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};
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template <typename BASE>
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riscv_hart_m_p<BASE>::riscv_hart_m_p()
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: state()
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, instr_if(*this) {
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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csr[marchid] = 0x80000003;
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csr[mimpid] = 1;
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uart_buf.str("");
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for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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}
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for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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}
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for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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csr_wr_cb[addr] = &this_class::write_reg;
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}
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for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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}
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for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
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csr_rd_cb[addr] = &this_class::read_null;
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//csr_wr_cb[addr] = &this_class::write_reg;
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}
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// common regs
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const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
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for(auto addr: addrs) {
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csr_rd_cb[addr] = &this_class::read_reg;
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csr_wr_cb[addr] = &this_class::write_reg;
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}
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// special handling & overrides
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csr_rd_cb[time] = &this_class::read_time;
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csr_rd_cb[timeh] = &this_class::read_time;
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csr_rd_cb[cycle] = &this_class::read_cycle;
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csr_rd_cb[cycleh] = &this_class::read_cycle;
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csr_rd_cb[instret] = &this_class::read_instret;
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csr_rd_cb[instreth] = &this_class::read_instret;
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csr_rd_cb[mcycle] = &this_class::read_cycle;
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csr_wr_cb[mcycle] = &this_class::write_cycle;
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csr_rd_cb[mcycleh] = &this_class::read_cycle;
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csr_wr_cb[mcycleh] = &this_class::write_cycle;
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csr_rd_cb[minstret] = &this_class::read_instret;
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csr_wr_cb[minstret] = &this_class::write_instret;
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csr_rd_cb[minstreth] = &this_class::read_instret;
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csr_wr_cb[minstreth] = &this_class::write_instret;
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csr_rd_cb[mstatus] = &this_class::read_status;
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csr_wr_cb[mstatus] = &this_class::write_status;
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csr_rd_cb[mip] = &this_class::read_ip;
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csr_wr_cb[mip] = &this_class::write_ip;
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[mhartid] = &this_class::read_hartid;
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csr_rd_cb[mcounteren] = &this_class::read_null;
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csr_wr_cb[mcounteren] = &this_class::write_null;
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csr_rd_cb[mtvec] = &this_class::read_mtvec;
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csr_wr_cb[mepc] = &this_class::write_mepc;
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csr_wr_cb[misa] = &this_class::write_null;
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csr_wr_cb[mvendorid] = &this_class::write_null;
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csr_wr_cb[marchid] = &this_class::write_null;
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csr_wr_cb[mimpid] = &this_class::write_null;
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}
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template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
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FILE *fp = fopen(name.c_str(), "r");
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if (fp) {
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std::array<char, 5> buf;
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auto n = fread(buf.data(), 1, 4, fp);
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if (n != 4) throw std::runtime_error("input file has insufficient size");
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buf[4] = 0;
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if (strcmp(buf.data() + 1, "ELF") == 0) {
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fclose(fp);
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// Create elfio reader
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ELFIO::elfio reader;
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// Load ELF data
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if (!reader.load(name)) throw std::runtime_error("could not process elf file");
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// check elf properties
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if (reader.get_class() != ELFCLASS32)
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if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file");
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if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file");
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if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file");
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for (const auto pseg : reader.segments) {
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const auto fsize = pseg->get_file_size(); // 0x42c/0x0
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const auto seg_data = pseg->get_data();
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if (fsize > 0) {
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
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traits<BASE>::MEM, pseg->get_physical_address(),
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fsize, reinterpret_cast<const uint8_t *const>(seg_data));
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if (res != iss::Ok)
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LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
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<< pseg->get_physical_address();
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}
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}
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for (const auto sec : reader.sections) {
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if (sec->get_name() == ".tohost") {
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tohost = sec->get_address();
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fromhost = tohost + 0x40;
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}
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}
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return std::make_pair(reader.get_entry(), true);
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}
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throw std::runtime_error("memory load file is not a valid elf file");
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}
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throw std::runtime_error("memory load file not found");
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}
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template <typename BASE>
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iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space,
|
|
const uint64_t addr, const unsigned length, uint8_t *const data) {
|
|
#ifndef NDEBUG
|
|
if (access && iss::access_type::DEBUG) {
|
|
LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
|
|
} else if(access && iss::access_type::FETCH){
|
|
LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr;
|
|
} else {
|
|
LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr;
|
|
}
|
|
#endif
|
|
try {
|
|
switch (space) {
|
|
case traits<BASE>::MEM: {
|
|
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
|
|
fault_data = addr;
|
|
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
|
|
this->reg.trap_state = (1 << 31); // issue trap 0
|
|
return iss::Err;
|
|
}
|
|
try {
|
|
auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
|
|
if(alignment>1 && (addr&(alignment-1))){
|
|
this->reg.trap_state = 1<<31 | 4<<16;
|
|
fault_data=addr;
|
|
return iss::Err;
|
|
}
|
|
auto res = type==iss::address_type::PHYSICAL?
|
|
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
|
|
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
|
|
if (unlikely(res != iss::Ok)){
|
|
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
|
|
fault_data=addr;
|
|
}
|
|
return res;
|
|
} catch (trap_access &ta) {
|
|
this->reg.trap_state = (1 << 31) | ta.id;
|
|
fault_data=ta.addr;
|
|
return iss::Err;
|
|
}
|
|
} break;
|
|
case traits<BASE>::CSR: {
|
|
if (length != sizeof(reg_t)) return iss::Err;
|
|
return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
|
|
} break;
|
|
case traits<BASE>::FENCE: {
|
|
if ((addr + length) > mem.size()) return iss::Err;
|
|
return iss::Ok;
|
|
} break;
|
|
case traits<BASE>::RES: {
|
|
auto it = atomic_reservation.find(addr);
|
|
if (it != atomic_reservation.end() && it->second != 0) {
|
|
memset(data, 0xff, length);
|
|
atomic_reservation.erase(addr);
|
|
} else
|
|
memset(data, 0, length);
|
|
} break;
|
|
default:
|
|
return iss::Err; // assert("Not supported");
|
|
}
|
|
return iss::Ok;
|
|
} catch (trap_access &ta) {
|
|
this->reg.trap_state = (1 << 31) | ta.id;
|
|
fault_data=ta.addr;
|
|
return iss::Err;
|
|
}
|
|
}
|
|
|
|
template <typename BASE>
|
|
iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space,
|
|
const uint64_t addr, const unsigned length, const uint8_t *const data) {
|
|
#ifndef NDEBUG
|
|
const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
|
|
switch (length) {
|
|
case 8:
|
|
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
|
|
<< ") @addr 0x" << std::hex << addr;
|
|
break;
|
|
case 4:
|
|
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec
|
|
<< ") @addr 0x" << std::hex << addr;
|
|
break;
|
|
case 2:
|
|
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec
|
|
<< ") @addr 0x" << std::hex << addr;
|
|
break;
|
|
case 1:
|
|
LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec
|
|
<< ") @addr 0x" << std::hex << addr;
|
|
break;
|
|
default:
|
|
LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
|
|
}
|
|
#endif
|
|
try {
|
|
switch (space) {
|
|
case traits<BASE>::MEM: {
|
|
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
|
|
fault_data = addr;
|
|
if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
|
|
this->reg.trap_state = (1 << 31); // issue trap 0
|
|
return iss::Err;
|
|
}
|
|
try {
|
|
if(length>1 && (addr&(length-1))){
|
|
this->reg.trap_state = 1<<31 | 6<<16;
|
|
fault_data=addr;
|
|
return iss::Err;
|
|
}
|
|
auto res = type==iss::address_type::PHYSICAL?
|
|
write_mem(phys_addr_t{access, space, addr}, length, data):
|
|
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
|
|
if (unlikely(res != iss::Ok)) {
|
|
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
|
|
fault_data=addr;
|
|
}
|
|
return res;
|
|
} catch (trap_access &ta) {
|
|
this->reg.trap_state = (1 << 31) | ta.id;
|
|
fault_data=ta.addr;
|
|
return iss::Err;
|
|
}
|
|
|
|
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
|
|
if ((paddr.val + length) > mem.size()) return iss::Err;
|
|
switch (paddr.val) {
|
|
case 0x10013000: // UART0 base, TXFIFO reg
|
|
case 0x10023000: // UART1 base, TXFIFO reg
|
|
uart_buf << (char)data[0];
|
|
if (((char)data[0]) == '\n' || data[0] == 0) {
|
|
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
|
// '"<<uart_buf.str()<<"'";
|
|
std::cout << uart_buf.str();
|
|
uart_buf.str("");
|
|
}
|
|
return iss::Ok;
|
|
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
|
auto &p = mem(paddr.val / mem.page_size);
|
|
auto offs = paddr.val & mem.page_addr_mask;
|
|
std::copy(data, data + length, p.data() + offs);
|
|
auto &x = *(p.data() + offs + 3);
|
|
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
|
|
return iss::Ok;
|
|
}
|
|
case 0x10008008: { // HFROSC base, pllcfg reg
|
|
auto &p = mem(paddr.val / mem.page_size);
|
|
auto offs = paddr.val & mem.page_addr_mask;
|
|
std::copy(data, data + length, p.data() + offs);
|
|
auto &x = *(p.data() + offs + 3);
|
|
x |= 0x80; // set pll lock upon writing
|
|
return iss::Ok;
|
|
} break;
|
|
default: {}
|
|
}
|
|
} break;
|
|
case traits<BASE>::CSR: {
|
|
if (length != sizeof(reg_t)) return iss::Err;
|
|
return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
|
|
} break;
|
|
case traits<BASE>::FENCE: {
|
|
if ((addr + length) > mem.size()) return iss::Err;
|
|
switch (addr) {
|
|
case 2:
|
|
case 3: {
|
|
ptw.clear();
|
|
auto tvm = state.mstatus.TVM;
|
|
return iss::Ok;
|
|
}
|
|
}
|
|
} break;
|
|
case traits<BASE>::RES: {
|
|
atomic_reservation[addr] = data[0];
|
|
} break;
|
|
default:
|
|
return iss::Err;
|
|
}
|
|
return iss::Ok;
|
|
} catch (trap_access &ta) {
|
|
this->reg.trap_state = (1 << 31) | ta.id;
|
|
fault_data=ta.addr;
|
|
return iss::Err;
|
|
}
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
|
|
if (addr >= csr.size()) return iss::Err;
|
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
|
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
auto it = csr_rd_cb.find(addr);
|
|
if (it == csr_rd_cb.end() || !it->second) // non existent register
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
return (this->*(it->second))(addr, val);
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
|
|
if (addr >= csr.size()) return iss::Err;
|
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
|
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
if((addr&0xc00)==0xc00) // writing to read-only region
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
auto it = csr_wr_cb.find(addr);
|
|
if (it == csr_wr_cb.end() || !it->second) // non existent register
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
return (this->*(it->second))(addr, val);
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
|
|
val = csr[addr];
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) {
|
|
val = 0;
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
|
|
csr[addr] = val;
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
|
|
auto cycle_val = this->reg.icount + cycle_offset;
|
|
if (addr == mcycle) {
|
|
val = static_cast<reg_t>(cycle_val);
|
|
} else if (addr == mcycleh) {
|
|
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
|
|
val = static_cast<reg_t>(cycle_val >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
|
|
if (sizeof(typename traits<BASE>::reg_t) != 4) {
|
|
if (addr == mcycleh)
|
|
return iss::Err;
|
|
mcycle_csr = static_cast<uint64_t>(val);
|
|
} else {
|
|
if (addr == mcycle) {
|
|
mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
|
|
} else {
|
|
mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
|
|
}
|
|
}
|
|
cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
|
|
if ((addr&0xff) == (minstret&0xff)) {
|
|
val = static_cast<reg_t>(this->reg.instret);
|
|
} else if ((addr&0xff) == (minstreth&0xff)) {
|
|
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
|
|
val = static_cast<reg_t>(this->reg.instret >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
|
|
if (sizeof(typename traits<BASE>::reg_t) != 4) {
|
|
if ((addr&0xff) == (minstreth&0xff))
|
|
return iss::Err;
|
|
this->reg.instret = static_cast<uint64_t>(val);
|
|
} else {
|
|
if ((addr&0xff) == (minstret&0xff)) {
|
|
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
|
|
} else {
|
|
this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff);
|
|
}
|
|
}
|
|
this->reg.instret--;
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
|
|
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
|
|
if (addr == time) {
|
|
val = static_cast<reg_t>(time_val);
|
|
} else if (addr == timeh) {
|
|
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
|
|
val = static_cast<reg_t>(time_val >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_mtvec(unsigned addr, reg_t &val) {
|
|
val = csr[mtvec] & ~2;
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
|
|
val = state.mstatus & hart_state_type::get_mask();
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
|
|
state.write_mstatus(val);
|
|
check_interrupt();
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
|
|
val = csr[mie];
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
|
|
val = mhartid_reg;
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
|
|
auto mask = get_irq_mask();
|
|
csr[mie] = (csr[mie] & ~mask) | (val & mask);
|
|
check_interrupt();
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
|
|
val = csr[mip];
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
|
|
auto mask = get_irq_mask();
|
|
mask &= ~(1 << 7); // MTIP is read only
|
|
csr[mip] = (csr[mip] & ~mask) | (val & mask);
|
|
check_interrupt();
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_mepc(unsigned addr, reg_t val) {
|
|
csr[addr] = val & get_pc_mask();
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE>
|
|
iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
|
|
if(mem_read_cb) return mem_read_cb(paddr, length, data);
|
|
switch (paddr.val) {
|
|
case 0x0200BFF8: { // CLINT base, mtime reg
|
|
if (sizeof(reg_t) < length) return iss::Err;
|
|
reg_t time_val;
|
|
this->read_csr(time, time_val);
|
|
std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
|
|
} break;
|
|
case 0x10008000: {
|
|
const mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
|
uint64_t offs = paddr.val & mem.page_addr_mask;
|
|
std::copy(p.data() + offs, p.data() + offs + length, data);
|
|
if (this->reg.icount > 30000) data[3] |= 0x80;
|
|
} break;
|
|
default: {
|
|
for(auto offs=0U; offs<length; ++offs) {
|
|
*(data + offs)=mem[(paddr.val+offs)%mem.size()];
|
|
}
|
|
}
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE>
|
|
iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
|
|
if(mem_write_cb) return mem_write_cb(paddr, length, data);
|
|
switch (paddr.val) {
|
|
case 0x10013000: // UART0 base, TXFIFO reg
|
|
case 0x10023000: // UART1 base, TXFIFO reg
|
|
uart_buf << (char)data[0];
|
|
if (((char)data[0]) == '\n' || data[0] == 0) {
|
|
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
|
|
// '"<<uart_buf.str()<<"'";
|
|
std::cout << uart_buf.str();
|
|
uart_buf.str("");
|
|
}
|
|
break;
|
|
case 0x10008000: { // HFROSC base, hfrosccfg reg
|
|
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
|
size_t offs = paddr.val & mem.page_addr_mask;
|
|
std::copy(data, data + length, p.data() + offs);
|
|
uint8_t &x = *(p.data() + offs + 3);
|
|
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
|
|
} break;
|
|
case 0x10008008: { // HFROSC base, pllcfg reg
|
|
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
|
size_t offs = paddr.val & mem.page_addr_mask;
|
|
std::copy(data, data + length, p.data() + offs);
|
|
uint8_t &x = *(p.data() + offs + 3);
|
|
x |= 0x80; // set pll lock upon writing
|
|
} break;
|
|
default: {
|
|
mem_type::page_type &p = mem(paddr.val / mem.page_size);
|
|
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
|
|
// tohost handling in case of riscv-test
|
|
if (paddr.access && iss::access_type::FUNC) {
|
|
auto tohost_upper = (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) ||
|
|
(traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
|
auto tohost_lower =
|
|
(traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
|
|
if (tohost_lower || tohost_upper) {
|
|
uint64_t hostvar = *reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask));
|
|
if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
|
|
switch (hostvar >> 48) {
|
|
case 0:
|
|
if (hostvar != 0x1) {
|
|
LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
|
<< "), stopping simulation";
|
|
} else {
|
|
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
|
<< "), stopping simulation";
|
|
}
|
|
this->reg.trap_state=std::numeric_limits<uint32_t>::max();
|
|
this->interrupt_sim=hostvar;
|
|
break;
|
|
//throw(iss::simulation_stopped(hostvar));
|
|
case 0x0101: {
|
|
char c = static_cast<char>(hostvar & 0xff);
|
|
if (c == '\n' || c == 0) {
|
|
LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
|
|
uart_buf.str("");
|
|
} else
|
|
uart_buf << c;
|
|
to_host_wr_cnt = 0;
|
|
} break;
|
|
default:
|
|
break;
|
|
}
|
|
} else if (tohost_lower)
|
|
to_host_wr_cnt++;
|
|
} else if ((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) ||
|
|
(traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
|
|
uint64_t fhostvar = *reinterpret_cast<uint64_t *>(p.data() + (fromhost & mem.page_addr_mask));
|
|
*reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) {
|
|
BASE::reset(address);
|
|
state.mstatus = hart_state_type::mstatus_reset_val;
|
|
}
|
|
|
|
template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
|
|
//auto ideleg = csr[mideleg];
|
|
// Multiple simultaneous interrupts and traps at the same privilege level are
|
|
// handled in the following decreasing priority order:
|
|
// external interrupts, software interrupts, timer interrupts, then finally
|
|
// any synchronous traps.
|
|
auto ena_irq = csr[mip] & csr[mie];
|
|
|
|
bool mie = state.mstatus.MIE;
|
|
auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
|
|
auto enabled_interrupts = m_enabled ? ena_irq : 0;
|
|
|
|
if (enabled_interrupts != 0) {
|
|
int res = 0;
|
|
while ((enabled_interrupts & 1) == 0) {
|
|
enabled_interrupts >>= 1;
|
|
res++;
|
|
}
|
|
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
|
|
}
|
|
}
|
|
|
|
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
|
|
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
|
|
// calculate and write mcause val
|
|
auto trap_id = bit_sub<0, 16>(flags);
|
|
auto cause = bit_sub<16, 15>(flags);
|
|
if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
|
|
// calculate effective privilege level
|
|
if (trap_id == 0) { // exception
|
|
// store ret addr in xepc register
|
|
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
|
|
csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
|
|
fault_data = 0;
|
|
} else {
|
|
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
|
|
this->reg.pending_trap = 0;
|
|
}
|
|
csr[mcause] = (trap_id << 31) + cause;
|
|
// update mstatus
|
|
// xPP field of mstatus is written with the active privilege mode at the time
|
|
// of the trap; the x PIE field of mstatus
|
|
// is written with the value of the active interrupt-enable bit at the time of
|
|
// the trap; and the x IE field of mstatus
|
|
// is cleared
|
|
// store the actual privilege level in yPP and store interrupt enable flags
|
|
state.mstatus.MPP = PRIV_M;
|
|
state.mstatus.MPIE = state.mstatus.MIE;
|
|
state.mstatus.MIE = false;
|
|
|
|
// get trap vector
|
|
auto ivec = csr[mtvec];
|
|
// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
|
|
// bits in mtvec
|
|
this->reg.NEXT_PC = ivec & ~0x3UL;
|
|
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
|
|
// reset trap state
|
|
this->reg.PRIV = PRIV_M;
|
|
this->reg.trap_state = 0;
|
|
std::array<char, 32> buffer;
|
|
sprintf(buffer.data(), "0x%016lx", addr);
|
|
if((flags&0xffffffff) != 0xffffffff)
|
|
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
|
|
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
|
|
<< " at address " << buffer.data() << " occurred";
|
|
return this->reg.NEXT_PC;
|
|
}
|
|
|
|
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
|
|
state.mstatus.MIE = state.mstatus.MPIE;
|
|
state.mstatus.MPIE = 1;
|
|
// sets the pc to the value stored in the x epc register.
|
|
this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
|
|
CLOG(INFO, disass) << "Executing xRET";
|
|
check_interrupt();
|
|
return this->reg.NEXT_PC;
|
|
}
|
|
|
|
} // namespace arch
|
|
} // namespace iss
|
|
|
|
#endif /* _RISCV_HART_M_P_H */
|