178 lines
6.1 KiB
Plaintext
178 lines
6.1 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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def nativeTypeSize(int size){
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if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
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}
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def getRegisterSizes(){
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def regs = registers.collect{nativeTypeSize(it.size)}
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regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
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return regs
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}
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def getRegisterOffsets(){
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def offset = 0
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def offsets = []
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getRegisterSizes().each { size ->
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offsets<<offset
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offset+=size/8
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}
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return offsets
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}
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def byteSize(int size){
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if(size<=8) return 8;
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if(size<=16) return 16;
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if(size<=32) return 32;
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if(size<=64) return 64;
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return 128;
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}
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def getCString(def val){
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return val.toString()+'ULL'
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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// clang-format off
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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namespace iss {
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namespace arch {
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struct ${coreDef.name.toLowerCase()};
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template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static char const* const core_type = "${coreDef.name}";
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static constexpr std::array<const char*, ${registers.size}> reg_names{
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{"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
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static constexpr std::array<const char*, ${registers.size}> reg_aliases{
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{"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
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enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {
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${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
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};
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using reg_t = uint${addrDataWidth}_t;
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using addr_t = uint${addrDataWidth}_t;
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using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
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{${getRegisterSizes().join(',')}}};
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static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
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{${getRegisterOffsets().join(',')}}};
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
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enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
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${instr.instruction.name} = ${index},<%}%>
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MAX_OPCODE
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};
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
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using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
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using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
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using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
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${coreDef.name.toLowerCase()}();
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~${coreDef.name.toLowerCase()}();
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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inline uint64_t get_icount() { return reg.icount; }
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inline bool should_stop() { return interrupt_sim; }
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inline uint64_t stop_code() { return interrupt_sim; }
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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inline uint32_t get_last_branch() { return reg.last_branch; }
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#pragma pack(push, 1)
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struct ${coreDef.name}_regs {<%
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registers.each { reg -> if(reg.size>0) {%>
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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}}%>
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uint32_t trap_state = 0, pending_trap = 0;
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uint64_t icount = 0;
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uint64_t cycle = 0;
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uint64_t instret = 0;
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uint32_t instruction = 0;
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uint32_t last_branch = 0;
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} reg;
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#pragma pack(pop)
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std::array<address_type, 4> addr_mode;
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uint64_t interrupt_sim=0;
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<%
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def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
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void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
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<%} else { %>
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uint32_t get_fcsr(){return 0;}
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void set_fcsr(uint32_t val){}
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<%}%>
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};
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}
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}
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#endif /* _${coreDef.name.toUpperCase()}_H_ */
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// clang-format on
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