117 lines
4.3 KiB
Plaintext
117 lines
4.3 KiB
Plaintext
import "RV32I.core_desc"
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InsructionSet RV64I extends RV32I {
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instructions{
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LWU { // 80000104: 0000ef03 lwu t5,0(ra)
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encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;
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args_disass:"{name(rd)}, {imm}({name(rs1)})";
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val offs[XLEN] <= X[rs1]'s+imm;
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if(rd!=0) X[rd]<=zext(MEM[offs]{32});
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}
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LD{
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encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
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args_disass:"{name(rd)}, {imm}({name(rs1)})";
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val offs[XLEN] <= X[rs1]'s + imm;
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if(rd!=0) X[rd]<=sext(MEM[offs]{64});
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}
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SD{
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011;
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args_disass:"{name(rs2)}, {imm}({name(rs1)})";
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val offs[XLEN] <= X[rs1]'s + imm;
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MEM[offs]{64} <= X[rs2];
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}
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SLLI {
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encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0) X[rd] <= shll(X[rs1], shamt);
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}
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SRLI {
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encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
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}
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SRAI {
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encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0) X[rd] <= shra(X[rs1], shamt);
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}
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ADDIW {
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
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args_disass:"{name(rd)}, {name(rs1)}, {imm}";
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if(rd != 0){
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val res[32] <= X[rs1]{32}'s + imm;
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X[rd] <= sext(res);
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}
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}
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SLLIW {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0){
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val sh_val[32] <= shll(X[rs1]{32}, shamt);
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X[rd] <= sext(sh_val);
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}
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}
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SRLIW {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0){
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val sh_val[32] <= shrl(X[rs1]{32}, shamt);
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X[rd] <= sext(sh_val);
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}
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}
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SRAIW {
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encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
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args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
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if(rd != 0){
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val sh_val[32] <= shra(X[rs1]{32}, shamt);
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X[rd] <= sext(sh_val);
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}
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}
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ADDW {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
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if(rd != 0){
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val res[32] <= X[rs1]{32} + X[rs2]{32};
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X[rd] <= sext(res);
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}
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}
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SUBW {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
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if(rd != 0){
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val res[32] <= X[rs1]{32} - X[rs2]{32};
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X[rd] <= sext(res);
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}
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}
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SLLW {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val mask[32] <= 0x1f;
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val count[32] <= X[rs2]{32} & mask;
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val sh_val[32] <= shll(X[rs1]{32}, count);
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X[rd] <= sext(sh_val);
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}
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}
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SRLW {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val mask[32] <= 0x1f;
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val count[32] <= X[rs2]{32} & mask;
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val sh_val[32] <= shrl(X[rs1]{32}, count);
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X[rd] <= sext(sh_val);
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}
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}
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SRAW {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val mask[32] <= 0x1f;
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val count[32] <= X[rs2]{32} & mask;
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val sh_val[32] <= shra(X[rs1]{32}, count);
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X[rd] <= sext(sh_val);
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}
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}
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}
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}
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