3679 lines
173 KiB
C++
3679 lines
173 KiB
C++
/*******************************************************************************
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* Copyright (C) 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "../fp_functions.h"
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#include <iss/arch/tgc_c.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/interp/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace interp {
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namespace tgc_c {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (super::tgt_adapter == nullptr)
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super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return super::tgt_adapter;
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}
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protected:
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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inline void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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}
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inline void wait(unsigned type){
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this->core.wait_until(type);
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}
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template<typename T>
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T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint8_t>(space, addr);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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return ret;
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}
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inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint16_t>(space, addr);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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return ret;
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}
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inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint32_t>(space, addr);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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return ret;
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}
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inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint64_t>(space, addr);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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return ret;
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}
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inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
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super::write_mem(space, addr, data);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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}
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
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super::write_mem(space, addr, data);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
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super::write_mem(space, addr, data);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
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super::write_mem(space, addr, data);
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if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
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}
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<InstructionDesriptor, 86> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */
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/* instruction LUI */
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{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
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/* instruction AUIPC */
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{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
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/* instruction JAL */
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{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
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/* instruction JALR */
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{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
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/* instruction BEQ */
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{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
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/* instruction BNE */
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{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
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/* instruction BLT */
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{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
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/* instruction BGE */
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{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
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/* instruction BLTU */
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{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
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/* instruction BGEU */
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{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
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/* instruction LB */
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{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
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/* instruction LH */
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{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
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/* instruction LW */
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{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
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/* instruction LBU */
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{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
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/* instruction LHU */
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{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
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/* instruction SB */
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{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
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/* instruction SH */
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{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
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/* instruction SW */
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{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
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/* instruction ADDI */
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{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
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/* instruction SLTI */
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{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
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/* instruction SLTIU */
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{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
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/* instruction XORI */
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{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
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/* instruction ORI */
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{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
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/* instruction ANDI */
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{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
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/* instruction SLLI */
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{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
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/* instruction SRLI */
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{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
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/* instruction SRAI */
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{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
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/* instruction ADD */
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{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
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/* instruction SUB */
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{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
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/* instruction SLL */
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{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
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/* instruction SLT */
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{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
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/* instruction SLTU */
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{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
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/* instruction XOR */
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{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
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/* instruction SRL */
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{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
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/* instruction SRA */
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{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
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/* instruction OR */
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{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
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/* instruction AND */
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{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
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/* instruction FENCE */
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{32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, &this_class::__fence},
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/* instruction ECALL */
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{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
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/* instruction EBREAK */
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{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
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/* instruction URET */
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{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
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/* instruction SRET */
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{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
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/* instruction MRET */
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{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
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/* instruction WFI */
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{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
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/* instruction CSRRW */
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{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
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/* instruction CSRRS */
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{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
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/* instruction CSRRC */
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{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
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/* instruction CSRRWI */
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{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
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/* instruction CSRRSI */
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{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
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/* instruction CSRRCI */
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{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
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/* instruction MUL */
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{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
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/* instruction MULH */
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{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
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/* instruction MULHSU */
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{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
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/* instruction MULHU */
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{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
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/* instruction DIV */
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{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
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/* instruction DIVU */
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{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
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/* instruction REM */
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{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
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/* instruction REMU */
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{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
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/* instruction CADDI4SPN */
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{16, 0b0000000000000000, 0b1110000000000011, &this_class::__caddi4spn},
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/* instruction CLW */
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{16, 0b0100000000000000, 0b1110000000000011, &this_class::__clw},
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/* instruction CSW */
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{16, 0b1100000000000000, 0b1110000000000011, &this_class::__csw},
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/* instruction CADDI */
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{16, 0b0000000000000001, 0b1110000000000011, &this_class::__caddi},
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/* instruction CNOP */
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{16, 0b0000000000000001, 0b1110111110000011, &this_class::__cnop},
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/* instruction CJAL */
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{16, 0b0010000000000001, 0b1110000000000011, &this_class::__cjal},
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/* instruction CLI */
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{16, 0b0100000000000001, 0b1110000000000011, &this_class::__cli},
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/* instruction CLUI */
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{16, 0b0110000000000001, 0b1110000000000011, &this_class::__clui},
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/* instruction CADDI16SP */
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{16, 0b0110000100000001, 0b1110111110000011, &this_class::__caddi16sp},
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/* instruction CSRLI */
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{16, 0b1000000000000001, 0b1111110000000011, &this_class::__csrli},
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/* instruction CSRAI */
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{16, 0b1000010000000001, 0b1111110000000011, &this_class::__csrai},
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/* instruction CANDI */
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{16, 0b1000100000000001, 0b1110110000000011, &this_class::__candi},
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/* instruction CSUB */
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{16, 0b1000110000000001, 0b1111110001100011, &this_class::__csub},
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/* instruction CXOR */
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{16, 0b1000110000100001, 0b1111110001100011, &this_class::__cxor},
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/* instruction COR */
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{16, 0b1000110001000001, 0b1111110001100011, &this_class::__cor},
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/* instruction CAND */
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{16, 0b1000110001100001, 0b1111110001100011, &this_class::__cand},
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/* instruction CJ */
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{16, 0b1010000000000001, 0b1110000000000011, &this_class::__cj},
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/* instruction CBEQZ */
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{16, 0b1100000000000001, 0b1110000000000011, &this_class::__cbeqz},
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/* instruction CBNEZ */
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{16, 0b1110000000000001, 0b1110000000000011, &this_class::__cbnez},
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/* instruction CSLLI */
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{16, 0b0000000000000010, 0b1111000000000011, &this_class::__cslli},
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/* instruction CLWSP */
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{16, 0b0100000000000010, 0b1110000000000011, &this_class::__clwsp},
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/* instruction CMV */
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{16, 0b1000000000000010, 0b1111000000000011, &this_class::__cmv},
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/* instruction CJR */
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{16, 0b1000000000000010, 0b1111000001111111, &this_class::__cjr},
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/* instruction CADD */
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{16, 0b1001000000000010, 0b1111000000000011, &this_class::__cadd},
|
|
/* instruction CJALR */
|
|
{16, 0b1001000000000010, 0b1111000001111111, &this_class::__cjalr},
|
|
/* instruction CEBREAK */
|
|
{16, 0b1001000000000010, 0b1111111111111111, &this_class::__cebreak},
|
|
/* instruction CSWSP */
|
|
{16, 0b1100000000000010, 0b1110000000000011, &this_class::__cswsp},
|
|
/* instruction DII */
|
|
{16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
|
|
}};
|
|
|
|
/* instruction definitions */
|
|
/* instruction 0: LUI */
|
|
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 0);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint32_t imm = ((bit_sub<12,20>(instr) << 12));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = (int32_t)imm;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 0);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 1: AUIPC */
|
|
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 1);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint32_t imm = ((bit_sub<12,20>(instr) << 12));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *PC + (int32_t)imm;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 1);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 2: JAL */
|
|
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 2);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) *(X+rd) = *PC + 4;
|
|
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 3: JALR */
|
|
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 3);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(rd != 0) *(X+rd) = *PC + 4;
|
|
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 3);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 4: BEQ */
|
|
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 4);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 5: BNE */
|
|
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 5);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 6: BLT */
|
|
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 6);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 7: BGE */
|
|
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 7);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 8: BLTU */
|
|
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 8);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 9: BGEU */
|
|
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 9);
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 10: LB */
|
|
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 10);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 10);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 11: LH */
|
|
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 11);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(traits::eei_aligned_addresses && (load_address & 0x1)) raise(0, 4);
|
|
else {
|
|
int16_t res = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 11);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 12: LW */
|
|
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 12);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(traits::eei_aligned_addresses && (load_address & 0x3)) raise(0, 4);
|
|
else {
|
|
int32_t res = (int32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
|
|
if(rd != 0) *(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 13: LBU */
|
|
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 13);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 13);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 14: LHU */
|
|
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 14);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(traits::eei_aligned_addresses && (load_address & 0x1)) raise(0, 4);
|
|
else {
|
|
uint16_t res = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 14);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 15: SB */
|
|
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 15);
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 16: SH */
|
|
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 16);
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(traits::eei_aligned_addresses && (store_address & 0x1)) raise(0, 6);
|
|
else writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 16);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 17: SW */
|
|
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 17);
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
if(traits::eei_aligned_addresses && (store_address & 0x3)) raise(0, 6);
|
|
else writeSpace4(traits::MEM, store_address, *(X+rs2));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 17);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 18: ADDI */
|
|
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 18);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 19: SLTI */
|
|
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 19);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 20: SLTIU */
|
|
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 20);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 21: XORI */
|
|
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 21);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 22: ORI */
|
|
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 22);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 23: ANDI */
|
|
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 23);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 24: SLLI */
|
|
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 24);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(shamt > 31) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) << shamt;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 24);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 25: SRLI */
|
|
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 25);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(shamt > 31) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 25);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 26: SRAI */
|
|
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 26);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(shamt > 31) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> shamt;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 26);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 27: ADD */
|
|
compile_ret_t __add(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 27);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) + *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 27);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 28: SUB */
|
|
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 28);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) - *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 28);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 29: SLL */
|
|
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 29);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 29);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 30: SLT */
|
|
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 30);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 30);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 31: SLTU */
|
|
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 31);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)? 1 : 0;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 31);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 32: XOR */
|
|
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 32);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) ^ *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 32);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 33: SRL */
|
|
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 33);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 33);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 34: SRA */
|
|
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 34);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 34);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 35: OR */
|
|
compile_ret_t __or(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 35);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) | *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 35);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 36: AND */
|
|
compile_ret_t __and(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 36);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
if(rd != 0) *(X+rd) = *(X+rs1) & *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 36);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 37: FENCE */
|
|
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 37);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t succ = ((bit_sub<20,4>(instr)));
|
|
uint8_t pred = ((bit_sub<24,4>(instr)));
|
|
uint8_t fm = ((bit_sub<28,4>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
|
|
fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
writeSpace1(traits::FENCE, traits::fence, pred << 4 | succ);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 37);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 38: ECALL */
|
|
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 38);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "ecall");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
raise(0, 11);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 38);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 39: EBREAK */
|
|
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 39);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "ebreak");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
raise(0, 3);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 39);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 40: URET */
|
|
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 40);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "uret");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
leave(0);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 40);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 41: SRET */
|
|
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 41);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "sret");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
leave(1);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 41);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 42: MRET */
|
|
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 42);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "mret");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
leave(3);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 42);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 43: WFI */
|
|
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 43);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "wfi");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
wait(1);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 43);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 44: CSRRW */
|
|
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 44);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rs_val = *(X+rs1);
|
|
if(rd != 0) {
|
|
uint32_t csr_val = readSpace4(traits::CSR, csr);
|
|
writeSpace4(traits::CSR, csr, rs_val);
|
|
*(X+rd) = csr_val;
|
|
}
|
|
else {
|
|
writeSpace4(traits::CSR, csr, rs_val);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 45: CSRRS */
|
|
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 45);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t xrd = readSpace4(traits::CSR, csr);
|
|
uint32_t xrs1 = *(X+rs1);
|
|
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1);
|
|
if(rd != 0) *(X+rd) = xrd;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 45);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 46: CSRRC */
|
|
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 46);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t xrd = readSpace4(traits::CSR, csr);
|
|
uint32_t xrs1 = *(X+rs1);
|
|
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1);
|
|
if(rd != 0) *(X+rd) = xrd;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 46);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 47: CSRRWI */
|
|
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 47);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) *(X+rd) = readSpace4(traits::CSR, csr);
|
|
writeSpace4(traits::CSR, csr, (uint32_t)zimm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 47);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 48: CSRRSI */
|
|
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 48);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t res = readSpace4(traits::CSR, csr);
|
|
if(zimm != 0) writeSpace4(traits::CSR, csr, res | (uint32_t)zimm);
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 48);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 49: CSRRCI */
|
|
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 49);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t res = readSpace4(traits::CSR, csr);
|
|
if(zimm != 0) writeSpace4(traits::CSR, csr, res & ~ ((uint32_t)zimm));
|
|
if(rd != 0) *(X+rd) = res;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 49);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 50: MUL */
|
|
compile_ret_t __mul(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 50);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 50);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 51: MULH */
|
|
compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 51);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
|
|
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 51);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 52: MULHSU */
|
|
compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 52);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
|
|
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 52);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 53: MULHU */
|
|
compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 53);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
|
|
*(X+rd) = (uint32_t)(res >> traits::XLEN);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 53);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 54: DIV */
|
|
compile_ret_t __div(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 54);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
if(*(X+rs2) != 0) {
|
|
uint32_t MMIN = 1 << (traits::XLEN - 1);
|
|
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN;
|
|
else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2);
|
|
}
|
|
else *(X+rd) = - 1;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 54);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 55: DIVU */
|
|
compile_ret_t __divu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 55);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2);
|
|
else *(X+rd) = - 1;
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 55);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 56: REM */
|
|
compile_ret_t __rem(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 56);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
if(*(X+rs2) != 0) {
|
|
uint32_t MMIN = 1 << (traits::XLEN - 1);
|
|
if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = 0;
|
|
else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
|
|
}
|
|
else *(X+rd) = *(X+rs1);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 56);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 57: REMU */
|
|
compile_ret_t __remu(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 57);
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) {
|
|
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2);
|
|
else *(X+rd) = *(X+rs1);
|
|
}
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 57);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 58: CADDI4SPN */
|
|
compile_ret_t __caddi4spn(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 58);
|
|
uint8_t rd = ((bit_sub<2,3>(instr)));
|
|
uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(imm == 0) raise(0, 2);
|
|
*(X+(rd + 8)) = *(X+2) + imm;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 58);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 59: CLW */
|
|
compile_ret_t __clw(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 59);
|
|
uint8_t rd = ((bit_sub<2,3>(instr)));
|
|
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
|
|
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t load_address = *(X+(rs1 + 8)) + uimm;
|
|
if(traits::eei_aligned_addresses && (load_address & 0x3)) raise(0, 4);
|
|
else *(X+(rd + 8)) = (int32_t)readSpace4(traits::MEM, load_address);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 59);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 60: CSW */
|
|
compile_ret_t __csw(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 60);
|
|
uint8_t rs2 = ((bit_sub<2,3>(instr)));
|
|
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
|
|
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t load_address = *(X+(rs1 + 8)) + uimm;
|
|
if(traits::eei_aligned_addresses && (load_address & 0x3)) raise(0, 6);
|
|
else writeSpace4(traits::MEM, load_address, *(X+(rs2 + 8)));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 60);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 61: CADDI */
|
|
compile_ret_t __caddi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 61);
|
|
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 61);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 62: CNOP */
|
|
compile_ret_t __cnop(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 62);
|
|
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "cnop");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 62);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 63: CJAL */
|
|
compile_ret_t __cjal(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 63);
|
|
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
|
|
fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
*(X+1) = *PC + 2;
|
|
pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 64: CLI */
|
|
compile_ret_t __cli(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 64);
|
|
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 64);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 65: CLUI */
|
|
compile_ret_t __clui(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 65);
|
|
uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
if(rd == 0) raise(0, 2);
|
|
if(imm == 0) raise(0, 2);
|
|
*(X+rd) = (int32_t)sext<18>(imm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 66: CADDI16SP */
|
|
compile_ret_t __caddi16sp(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 66);
|
|
uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
|
|
fmt::arg("nzimm", nzimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
|
|
else raise(0, 2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 67: CSRLI */
|
|
compile_ret_t __csrli(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 67);
|
|
uint8_t shamt = ((bit_sub<2,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
|
|
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rs1_idx = rs1 + 8;
|
|
*(X+rs1_idx) = *(X+rs1_idx) >> shamt;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 68: CSRAI */
|
|
compile_ret_t __csrai(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 68);
|
|
uint8_t shamt = ((bit_sub<2,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
|
|
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(shamt) {
|
|
uint32_t rs1_idx = rs1 + 8;
|
|
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt;
|
|
}
|
|
else if(traits::XLEN == 128) {
|
|
uint32_t rs1_idx = rs1 + 8;
|
|
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> 64;
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 69: CANDI */
|
|
compile_ret_t __candi(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 69);
|
|
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
|
|
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rs1_idx = rs1 + 8;
|
|
*(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 69);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 70: CSUB */
|
|
compile_ret_t __csub(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 70);
|
|
uint8_t rs2 = ((bit_sub<2,3>(instr)));
|
|
uint8_t rd = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
|
|
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rd_idx = rd + 8;
|
|
*(X+rd_idx) = *(X+rd_idx) - *(X+(rs2 + 8));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 70);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 71: CXOR */
|
|
compile_ret_t __cxor(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 71);
|
|
uint8_t rs2 = ((bit_sub<2,3>(instr)));
|
|
uint8_t rd = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
|
|
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rd_idx = rd + 8;
|
|
*(X+rd_idx) = *(X+rd_idx) ^ *(X+(rs2 + 8));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 72: COR */
|
|
compile_ret_t __cor(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 72);
|
|
uint8_t rs2 = ((bit_sub<2,3>(instr)));
|
|
uint8_t rd = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
|
|
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rd_idx = rd + 8;
|
|
*(X+rd_idx) = *(X+rd_idx) | *(X+(rs2 + 8));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 72);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 73: CAND */
|
|
compile_ret_t __cand(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 73);
|
|
uint8_t rs2 = ((bit_sub<2,3>(instr)));
|
|
uint8_t rd = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
|
|
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t rd_idx = rd + 8;
|
|
*(X+rd_idx) = *(X+rd_idx) & *(X+(rs2 + 8));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 73);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 74: CJ */
|
|
compile_ret_t __cj(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 74);
|
|
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
|
|
fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 74);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 75: CBEQZ */
|
|
compile_ret_t __cbeqz(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 75);
|
|
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
|
|
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 75);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 76: CBNEZ */
|
|
compile_ret_t __cbnez(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 76);
|
|
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
|
|
uint8_t rs1 = ((bit_sub<7,3>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
|
|
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 77: CSLLI */
|
|
compile_ret_t __cslli(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 77);
|
|
uint8_t nzuimm = ((bit_sub<2,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm;
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 78: CLWSP */
|
|
compile_ret_t __clwsp(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 78);
|
|
uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(rd) {
|
|
uint32_t offs = *(X+2) + uimm;
|
|
*(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
|
|
}
|
|
else raise(0, 2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 79: CMV */
|
|
compile_ret_t __cmv(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 79);
|
|
uint8_t rs2 = ((bit_sub<2,5>(instr)));
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
*(X+rd) = *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 79);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 80: CJR */
|
|
compile_ret_t __cjr(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 80);
|
|
uint8_t rs1 = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
|
|
fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
if(rs1) pc_assign(*NEXT_PC) = *(X+rs1);
|
|
else raise(0, 2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 80);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 81: CADD */
|
|
compile_ret_t __cadd(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 81);
|
|
uint8_t rs2 = ((bit_sub<2,5>(instr)));
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
*(X+rd) = *(X+rd) + *(X+rs2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 81);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 82: CJALR */
|
|
compile_ret_t __cjalr(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 82);
|
|
uint8_t rs1 = ((bit_sub<7,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
|
|
fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
*(X+1) = *PC + 2;
|
|
pc_assign(*NEXT_PC) = *(X+rs1);
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 82);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 83: CEBREAK */
|
|
compile_ret_t __cebreak(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 83);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "cebreak");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
raise(0, 3);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 83);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 84: CSWSP */
|
|
compile_ret_t __cswsp(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 84);
|
|
uint8_t rs2 = ((bit_sub<2,5>(instr)));
|
|
uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers
|
|
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
{
|
|
uint32_t offs = *(X+2) + uimm;
|
|
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
|
|
}
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 84);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/* instruction 85: DII */
|
|
compile_ret_t __dii(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
this->do_sync(PRE_SYNC, 85);
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "dii");
|
|
|
|
}
|
|
// prepare execution
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 2;
|
|
// execute instruction
|
|
try {
|
|
raise(0, 2);
|
|
} catch(...){}
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85);
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* end opcode definitions
|
|
****************************************************************************/
|
|
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
|
|
this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
|
|
raise(0, 2);
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
|
|
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
|
|
auto phys_pc = this->core.v2p(pc);
|
|
//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
|
// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
|
|
// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
|
|
// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
|
|
//} else {
|
|
if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
|
|
//}
|
|
return iss::Ok;
|
|
}
|
|
};
|
|
|
|
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
|
volatile CODE_WORD x = insn;
|
|
insn = 2 * x;
|
|
}
|
|
|
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
|
|
|
template <typename ARCH>
|
|
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
|
: vm_base<ARCH>(core, core_id, cluster_id) {
|
|
qlut[0] = lut_00.data();
|
|
qlut[1] = lut_01.data();
|
|
qlut[2] = lut_10.data();
|
|
qlut[3] = lut_11.data();
|
|
for (auto instr : instr_descr) {
|
|
auto quantrant = instr.value & 0x3;
|
|
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
|
}
|
|
}
|
|
|
|
inline bool is_count_limit_enabled(finish_cond_e cond){
|
|
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
|
|
}
|
|
template <typename ARCH>
|
|
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
|
|
// we fetch at max 4 byte, alignment is 2
|
|
enum {TRAP_ID=1<<16};
|
|
code_word_t insn = 0;
|
|
auto *const data = (uint8_t *)&insn;
|
|
auto pc=start;
|
|
while(!this->core.should_stop() &&
|
|
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
|
|
auto res = fetch_ins(pc, data);
|
|
if(res!=iss::Ok){
|
|
auto new_pc = super::core.enter_trap(TRAP_ID, pc.val);
|
|
res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
|
|
if(res!=iss::Ok) throw simulation_stopped(0);
|
|
}
|
|
if ((cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF &&
|
|
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
|
auto lut_val = extract_fields(insn);
|
|
auto f = qlut[insn & 0x3][lut_val];
|
|
if (!f)
|
|
f = &this_class::illegal_intruction;
|
|
pc = (this->*f)(pc, insn);
|
|
}
|
|
return pc;
|
|
}
|
|
|
|
} // namespace mnrv32
|
|
|
|
template <>
|
|
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
|
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
return std::unique_ptr<vm_if>(ret);
|
|
}
|
|
} // namespace interp
|
|
} // namespace iss
|