323 lines
14 KiB
C++
323 lines
14 KiB
C++
/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/arch/CORE_DEF_NAME.h>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/llvm/vm_base.h>
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#include <util/logging.h>
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#include <boost/format.hpp>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace vm {
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namespace fp_impl {
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void add_fp_functions_2_module(llvm::Module *, unsigned);
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}
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}
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namespace CORE_DEF_NAME {
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using namespace iss::arch;
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using namespace llvm;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
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public:
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using super = typename vm::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
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vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm::vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm::vm_base<ARCH>::get_reg_ptr;
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template <typename T> inline llvm::ConstantInt *size(T type) {
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return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
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}
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void setup_module(llvm::Module *m) override {
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super::setup_module(m);
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vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
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}
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inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) {
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return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
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}
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std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
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llvm::BasicBlock *) override;
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void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
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void gen_raise_trap(uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(unsigned lvl);
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void gen_wait(unsigned type);
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void gen_trap_behavior(llvm::BasicBlock *) override;
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void gen_trap_check(llvm::BasicBlock *bb);
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inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
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return this->builder.CreateLoad(get_reg_ptr(i), false);
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}
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inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
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llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
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this->get_type(traits<ARCH>::XLEN));
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this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
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}
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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using this_class = vm_impl<ARCH>;
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using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
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code_word_t instr,
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llvm::BasicBlock *bb);
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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/* «start generated code» */
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std::array<InstructionDesriptor, 0> instr_descr = {{}};
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/* «end generated code» */
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
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llvm::BasicBlock *bb) {
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this->gen_sync(iss::PRE_SYNC, instr_descr.size());
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this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
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get_reg_ptr(traits<ARCH>::PC), true);
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this->builder.CreateStore(
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this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
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this->gen_const(64U, 1)),
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get_reg_ptr(traits<ARCH>::ICOUNT), true);
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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this->gen_raise_trap(0, 2); // illegal instruction trap
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this->gen_sync(iss::POST_SYNC, instr_descr.size());
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this->gen_trap_check(this->leave_blk);
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return std::make_tuple(iss::vm::BRANCH, nullptr);
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
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volatile CODE_WORD x = insn;
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insn = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm::vm_base<ARCH>(core, core_id, cluster_id) {
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qlut[0] = lut_00.data();
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qlut[1] = lut_01.data();
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qlut[2] = lut_10.data();
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qlut[3] = lut_11.data();
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for (auto instr : instr_descr) {
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auto quantrant = instr.value & 0x3;
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expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
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}
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}
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template <typename ARCH>
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std::tuple<vm::continuation_e, llvm::BasicBlock *>
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
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// we fetch at max 4 byte, alignment is 2
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code_word_t insn = 0;
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const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
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phys_addr_t paddr(pc);
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try {
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auto *const data = (uint8_t *)&insn;
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paddr = this->core.v2p(pc);
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if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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auto res = this->core.read(paddr, 2, data);
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if (res != iss::Ok) throw trap_access(1, pc.val);
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if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
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res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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}
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} else {
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok) throw trap_access(1, pc.val);
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}
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} catch (trap_access &ta) {
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throw trap_access(ta.id, pc.val);
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}
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if (insn == 0x0000006f || (insn & 0xffff) == 0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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++inst_cnt;
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auto lut_val = extract_fields(insn);
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auto f = qlut[insn & 0x3][lut_val];
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if (f == nullptr) {
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f = &this_class::illegal_intruction;
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}
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return (this->*f)(pc, insn, this_block);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock *leave_blk) {
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this->builder.SetInsertPoint(leave_blk);
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this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
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auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
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this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
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this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
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get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
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std::vector<llvm::Value *> args{
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this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
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};
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this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
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auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
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this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
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this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
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get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
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std::vector<llvm::Value *> args{
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this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
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};
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this->builder.CreateCall(this->mod->getFunction("wait"), args);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
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this->builder.SetInsertPoint(trap_blk);
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auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
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this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
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get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
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std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
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this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
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this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
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auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
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this->builder.CreateRet(trap_addr_val);
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}
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template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock *bb) {
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auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
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this->gen_cond_branch(this->builder.CreateICmp(
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ICmpInst::ICMP_EQ, v,
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llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
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bb, this->trap_blk, 1);
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}
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} // namespace CORE_DEF_NAME
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template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) {
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auto ret = new CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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} // namespace iss
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