449 lines
14 KiB
C++
449 lines
14 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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////////////////////////////////////////////////////////////////////////////////
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#include "fp_functions.h"
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extern "C" {
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#include <softfloat.h>
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#include "internals.h"
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#include "specialize.h"
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}
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#include <limits>
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using this_t = uint8_t *;
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const uint8_t rmm_map[] = {
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softfloat_round_near_even /*RNE*/,
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softfloat_round_minMag/*RTZ*/,
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softfloat_round_min/*RDN*/,
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softfloat_round_max/*RUP?*/,
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softfloat_round_near_maxMag /*RMM*/,
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softfloat_round_max/*RTZ*/,
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softfloat_round_max/*RTZ*/,
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softfloat_round_max/*RTZ*/,
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};
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const uint32_t quiet_nan32=0x7fC00000;
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extern "C" {
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uint32_t fget_flags(){
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return softfloat_exceptionFlags&0x1f;
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}
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uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r =f32_add(v1f, v2f);
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return r.v;
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}
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uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_sub(v1f, v2f);
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return r.v;
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}
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uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_mul(v1f, v2f);
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return r.v;
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}
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uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) {
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float32_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_div(v1f, v2f);
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return r.v;
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}
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uint32_t fsqrt_s(uint32_t v1, uint8_t mode) {
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float32_t v1f{v1};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t r=f32_sqrt(v1f);
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return r.v;
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}
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uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
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float32_t v1f{v1},v2f{v2};
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softfloat_exceptionFlags=0;
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bool nan = (v1&defaultNaNF32UI)==quiet_nan32 || (v2&defaultNaNF32UI)==quiet_nan32;
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bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2);
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switch(op){
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case 0:
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if(nan | snan){
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if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_eq(v1f,v2f )?1:0;
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case 1:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_le(v1f,v2f )?1:0;
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case 2:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f32_lt(v1f,v2f )?1:0;
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default:
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break;
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}
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return -1;
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}
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uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
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float32_t v1f{v1};
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softfloat_exceptionFlags=0;
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float32_t r;
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switch(op){
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case 0:{ //w->s, fp to int32
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uint_fast32_t res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
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return (uint32_t)res;
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}
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case 1:{ //wu->s
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uint_fast32_t res = f32_to_ui32(v1f,rmm_map[mode&0x7],true);
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return (uint32_t)res;
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}
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case 2: //s->w
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r=i32_to_f32(v1);
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return r.v;
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case 3: //s->wu
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r=ui32_to_f32(v1);
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return r.v;
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}
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return 0;
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}
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uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) {
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// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
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if(op>1) res.v ^= 1ULL<<31;
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return res.v;
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}
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uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
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softfloat_exceptionFlags = 0;
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bool v1_nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
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bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
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bool v1_snan = softfloat_isSigNaNF32UI(v1);
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bool v2_snan = softfloat_isSigNaNF32UI(v2);
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if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
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if (v1_nan || v1_snan)
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return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
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else
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if (v2_nan || v2_snan)
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return v1;
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else {
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if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
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return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1);
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} else {
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float32_t v1f{ v1 }, v2f{ v2 };
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return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1);
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}
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}
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}
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uint32_t fclass_s( uint32_t v1 ){
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float32_t a{v1};
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union ui32_f32 uA;
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uint_fast32_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
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uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
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bool sign = signF32UI( uiA );
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bool fracZero = fracF32UI( uiA ) == 0;
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bool isNaN = isNaNF32UI( uiA );
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bool isSNaN = softfloat_isSigNaNF32UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
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softfloat_roundingMode=rmm_map[mode&0x7];
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bool nan = (v1 & defaultNaNF64UI)==defaultNaNF64UI;
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if(nan){
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return defaultNaNF32UI;
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} else {
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float32_t res = f64_to_f32(float64_t{v1});
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return res.v;
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}
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}
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uint64_t fconv_f2d(uint32_t v1, uint8_t mode){
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bool nan = (v1 & defaultNaNF32UI)==defaultNaNF32UI;
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if(nan){
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return defaultNaNF64UI;
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} else {
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softfloat_roundingMode=rmm_map[mode&0x7];
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float64_t res = f32_to_f64(float32_t{v1});
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return res.v;
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}
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}
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uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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bool nan = (v1&defaultNaNF32UI)==quiet_nan32;
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bool snan = softfloat_isSigNaNF32UI(v1);
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r =f64_add(v1f, v2f);
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return r.v;
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}
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uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r=f64_sub(v1f, v2f);
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return r.v;
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}
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uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r=f64_mul(v1f, v2f);
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return r.v;
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}
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uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode) {
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float64_t v1f{v1},v2f{v2};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r=f64_div(v1f, v2f);
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return r.v;
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}
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uint64_t fsqrt_d(uint64_t v1, uint8_t mode) {
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float64_t v1f{v1};
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t r=f64_sqrt(v1f);
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return r.v;
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}
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uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
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float64_t v1f{v1},v2f{v2};
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softfloat_exceptionFlags=0;
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bool nan = (v1&defaultNaNF64UI)==quiet_nan32 || (v2&defaultNaNF64UI)==quiet_nan32;
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bool snan = softfloat_isSigNaNF64UI(v1) || softfloat_isSigNaNF64UI(v2);
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switch(op){
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case 0:
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if(nan | snan){
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if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f64_eq(v1f,v2f )?1:0;
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case 1:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f64_le(v1f,v2f )?1:0;
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case 2:
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if(nan | snan){
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softfloat_raiseFlags(softfloat_flag_invalid);
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return 0;
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} else
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return f64_lt(v1f,v2f )?1:0;
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default:
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break;
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}
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return -1;
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}
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uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
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float64_t v1f{v1};
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softfloat_exceptionFlags=0;
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float64_t r;
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switch(op){
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case 0:{ //l->d, fp to int32
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int64_t res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
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return (uint64_t)res;
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}
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case 1:{ //lu->s
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uint64_t res = f64_to_ui64(v1f,rmm_map[mode&0x7],true);
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return res;
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}
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case 2: //s->l
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r=i64_to_f64(v1);
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return r.v;
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case 3: //s->lu
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r=ui64_to_f64(v1);
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return r.v;
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}
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return 0;
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}
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uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
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// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
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softfloat_roundingMode=rmm_map[mode&0x7];
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softfloat_exceptionFlags=0;
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float64_t res = softfloat_mulAddF64(v1, v2, v3, op&0x1);
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if(op>1) res.v ^= 1ULL<<63;
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return res.v;
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}
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uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
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softfloat_exceptionFlags = 0;
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bool v1_nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
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bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
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bool v1_snan = softfloat_isSigNaNF64UI(v1);
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bool v2_snan = softfloat_isSigNaNF64UI(v2);
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if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
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if (v1_nan || v1_snan)
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return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
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else
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if (v2_nan || v2_snan)
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return v1;
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else {
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if ((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
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return op == 0 ?
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((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
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((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
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} else {
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float64_t v1f{ v1 }, v2f{ v2 };
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return op == 0 ?
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(f64_lt(v1f, v2f) ? v1 : v2) :
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(f64_lt(v1f, v2f) ? v2 : v1);
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}
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}
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}
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uint64_t fclass_d(uint64_t v1 ){
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float64_t a{v1};
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union ui64_f64 uA;
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uint_fast64_t uiA;
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uA.f = a;
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uiA = uA.ui;
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uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
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uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
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bool sign = signF64UI( uiA );
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bool fracZero = fracF64UI( uiA ) == 0;
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bool isNaN = isNaNF64UI( uiA );
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bool isSNaN = softfloat_isSigNaNF64UI( uiA );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
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float32_t v1f{v1};
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softfloat_exceptionFlags=0;
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float64_t r;
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switch(op){
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case 0: //l->s, fp to int32
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return f32_to_i64(v1f,rmm_map[mode&0x7],true);
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case 1: //wu->s
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return f32_to_ui64(v1f,rmm_map[mode&0x7],true);
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case 2: //s->w
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r=i32_to_f64(v1);
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return r.v;
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case 3: //s->wu
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r=ui32_to_f64(v1);
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return r.v;
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}
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return 0;
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}
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uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode) {
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softfloat_exceptionFlags=0;
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float32_t r;
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switch(op){
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case 0:{ //wu->s
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int32_t r=f64_to_i32(float64_t{v1}, rmm_map[mode&0x7],true);
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return r;
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}
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case 1:{ //wu->s
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uint32_t r=f64_to_ui32(float64_t{v1}, rmm_map[mode&0x7],true);
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return r;
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}
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case 2: //l->s, fp to int32
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r=i64_to_f32(v1);
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return r.v;
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case 3: //wu->s
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r=ui64_to_f32(v1);
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return r.v;
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}
|
|
return 0;
|
|
}
|
|
|
|
uint32_t unbox_s(uint64_t v){
|
|
constexpr uint64_t mask = std::numeric_limits<uint64_t>::max() & ~((uint64_t)std::numeric_limits<uint32_t>::max());
|
|
if((v & mask) != mask)
|
|
return 0x7fc00000;
|
|
else
|
|
return v & std::numeric_limits<uint32_t>::max();
|
|
}
|
|
}
|
|
|