355 lines
9.8 KiB
Plaintext
355 lines
9.8 KiB
Plaintext
import "RV32IBase.core_desc"
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InsructionSet RV32IC {
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constants {
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XLEN
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}
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address_spaces {
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MEM[8]
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}
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registers {
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[31:0] X[XLEN],
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PC[XLEN](is_pc)
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}
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instructions{
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JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
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args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
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if(rd!=0) X[rd] <= PC+4;
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val ret[XLEN] <= X[rs1]+ imm;
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PC<=ret& ~0x1;
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}
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C.ADDI4SPN { //(RES, imm=0)
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encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
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args_disass: "x%rd$d, 0x%imm$05x";
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if(imm == 0) raise(0, 2);
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val rd_idx[5] <= rd+8;
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val x2_idx[5] <= 2;
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X[rd_idx] <= X[x2_idx] + imm;
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}
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C.LW { // (RV32)
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encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
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args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x";
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val rs1_idx[5] <= rs1+8;
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val rd_idx[5] <= rd+8;
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val offs[XLEN] <= X[rs1_idx]+uimm;
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X[rd_idx] <= MEM[offs]{32};
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}
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C.SW {//(RV32)
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encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
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args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x";
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val rs1_idx[5] <= rs1+8;
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val rs2_idx[5] <= rs2+8;
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val offs[XLEN] <= X[rs1_idx]+uimm;
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MEM[offs]{32} <= X[rs2_idx];
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}
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C.ADDI {//(RV32)
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encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
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args_disass: "x%rs1$d, 0x%imm$05x";
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X[rs1] <= X[rs1] + imm;
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}
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C.NOP {
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encoding:b000 | b0 | b00000 | b00000 | b01;
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}
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// C.JAL will be overwritten by C.ADDIW for RV64/128
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C.JAL(no_cont) {//(RV32)
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encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
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args_disass: "0x%imm$05x";
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val rd[5] <= 1;
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X[rd] <= PC+2;
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PC<=PC+imm;
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}
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C.LI {//(RV32)
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encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
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args_disass: "x%rd$d, 0x%imm$05x";
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if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
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X[rd] <= imm;
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}
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// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
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C.LUI {//(RV32)
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encoding:b011 | imm[17:17]s | rd[4:0] | imm[16:12]s | b01;
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args_disass: "x%rd$d, 0x%imm$05x";
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if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
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if(imm == 0) raise(0, 2); //TODO: should it be handled as trap?
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X[rd] <= imm;
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}
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C.ADDI16SP {//(RV32)
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encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
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args_disass: "0x%imm$05x";
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val x2_idx[5] <= 2;
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X[x2_idx] <= X[x2_idx]s + imm;
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}
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C.SRLI {//(RV32 nse)
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encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "x(8+%rs1$d), %shamt$d";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shrl(X[rs1_idx], shamt);
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}
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C.SRAI {//(RV32)
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encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
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args_disass: "x(8+%rs1$d), %shamt$d";
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val rs1_idx[5] <= rs1+8;
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X[rs1_idx] <= shra(X[rs1_idx], shamt);
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}
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C.ANDI {//(RV32)
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encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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val rs1_idx[5] <= rs1 + 8;
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X[rs1_idx] <= X[rs1_idx] & imm;
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}
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C.SUB {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
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args_disass: "x(8+%rd$d), x(8+%rs2$d)";
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val rd_idx[5] <= rd + 8;
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val rs2_idx[5] <= rs2 + 8;
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X[rd_idx] <= X[rd_idx] - X[rs2_idx];
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}
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C.XOR {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
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args_disass: "x(8+%rd$d), x(8+%rs2$d)";
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val rd_idx[5] <= rd + 8;
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val rs2_idx[5] <= rs2 + 8;
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X[rd_idx] <= X[rd_idx] ^ X[rs2_idx];
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}
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C.OR {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
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args_disass: "x(8+%rd$d), x(8+%rs2$d)";
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val rd_idx[5] <= rd + 8;
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val rs2_idx[5] <= rs2 + 8;
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X[rd_idx] <= X[rd_idx] | X[rs2_idx];
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}
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C.AND {//(RV32)
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encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
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args_disass: "x(8+%rd$d), x(8+%rs2$d)";
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val rd_idx[5] <= rd + 8;
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val rs2_idx[5] <= rs2 + 8;
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X[rd_idx] <= X[rd_idx] & X[rs2_idx];
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}
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C.J(no_cont) {//(RV32)
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encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
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args_disass: "0x%imm$05x";
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PC<=PC+imm;
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}
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C.BEQZ(no_cont,cond) {//(RV32)
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encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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val rs1_idx[5] <= rs1+8;
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PC<=choose(X[rs1_idx]==0, PC+imm, PC+2);
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}
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C.BNEZ(no_cont,cond) {//(RV32)
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encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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val rs1_idx[5] <= rs1+8;
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PC<=choose(X[rs1_idx]!=0, PC+imm, PC+2);
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}
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C.SLLI {//(RV32)
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encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
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args_disass: "x%rs1$d, %shamt$d";
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if(rs1 == 0) raise(0, 2);
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X[rs1] <= shll(X[rs1], shamt);
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}
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C.LWSP {//
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encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
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args_disass: "x%rd$d, sp, 0x%uimm$05x";
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val x2_idx[5] <= 2;
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val offs[XLEN] <= X[x2_idx] + uimm;
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X[rd] <= MEM[offs]{32};
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}
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// order matters as C.JR is a special case of C.MV
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C.MV {//(RV32)
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encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
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args_disass: "x%rd$d, x%rs2$d";
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X[rd] <= X[rs2];
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}
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C.JR(no_cont) {//(RV32)
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encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
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args_disass: "x%rs1$d";
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PC <= X[rs1];
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}
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// order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD
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C.ADD {//(RV32)
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encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
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args_disass: "x%rd$d, x%rs2$d";
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X[rd] <= X[rd] + X[rs2];
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}
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C.JALR(no_cont) {//(RV32)
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encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
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args_disass: "x%rs1$d";
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val r_idx[5] <= 1;
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X[r_idx] <= PC+2;
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PC<=X[rs1];
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}
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C.EBREAK(no_cont) {//(RV32)
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encoding:b100 | b1 | b00000 | b00000 | b10;
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raise(0, 3);
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}
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C.SWSP {//
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encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
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args_disass: "x2+0x%uimm$05x, x%rs2$d";
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val x2_idx[5] <= 2;
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val offs[XLEN] <= X[x2_idx] + uimm;
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MEM[offs]{32} <= X[rs2];
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}
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DII {
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encoding:b000 | b0 | b00000 | b00000 | b00;
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raise(0, 2);
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}
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}
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}
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InsructionSet RV32FC extends RV32IC{
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constants {
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XLEN, FLEN
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}
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address_spaces {
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MEM[8]
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}
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registers {
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[31:0] X[XLEN],
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[31:0] F[FLEN]
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}
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instructions{
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C.FLW {
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encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
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args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
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val rs1_idx[5] <= rs1+8;
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val rd_idx[5] <= rd+8;
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val offs[XLEN] <= X[rs1_idx]+uimm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd_idx] <= res;
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else {
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val upper[FLEN] <= (-1<<31);
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F[rd_idx] <= upper*2 | res;
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}
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}
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C.FSW {
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encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
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args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
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val rs1_idx[5] <= rs1+8;
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val rs2_idx[5] <= rs2+8;
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val offs[XLEN] <= X[rs1_idx]+uimm;
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MEM[offs]{32}<=F[rs2_idx]{32};
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}
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C.FLWSP {
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encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
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args_disass:"f%rd$d, %uimm%(x2)";
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val x2_idx[5] <= 2;
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val offs[XLEN] <= X[x2_idx]+uimm;
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val res[32] <= MEM[offs]{32};
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if(FLEN==32)
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F[rd] <= res;
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else {
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val upper[FLEN] <= (-1<<31);
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F[rd] <= upper*2 | res;
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}
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}
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C.FSWSP {
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encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
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args_disass:"f%rs2$d, %uimm%(x2), ";
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val x2_idx[5] <= 2;
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val offs[XLEN] <= X[x2_idx]+uimm;
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MEM[offs]{32}<=F[rs2];
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}
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}
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}
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InsructionSet RV32DC extends RV32IC{
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constants {
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XLEN, FLEN
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}
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address_spaces {
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MEM[8]
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}
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registers {
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[31:0] X[XLEN],
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[31:0] F[FLEN]
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}
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instructions{
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C.FLD { //(RV32/64)
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encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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}
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C.FSD { //(RV32/64)
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encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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}
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C.FLDSP {//(RV32/64)
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encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
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}
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C.FSDSP {//(RV32/64)
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encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
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}
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}
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}
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InsructionSet RV64IC extends RV32IC {
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constants {
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XLEN
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}
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address_spaces {
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MEM[8]
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}
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registers {
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[31:0] X[XLEN],
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PC[XLEN](is_pc)
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}
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instructions{
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C.LD {//(RV64/128)
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encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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}
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C.SD { //(RV64/128)
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encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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}
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C.SUBW {//(RV64/128, RV32 res)
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encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
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args_disass: "x%rd$d, sp, 0x%imm$05x";
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}
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C.ADDW {//(RV64/128 RV32 res)
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encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
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args_disass: "x%rd$d, sp, 0x%imm$05x";
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}
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C.ADDIW {//(RV64/128)
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encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01;
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}
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C.SRLI64 {//(RV32/64/128)
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encoding:b100 | b0 | b00 | rs1[2:0] | b00000 | b01;
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}
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C.SRAI64 {//(RV32/64/128)
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encoding:b100 | b0 | b01 | rs1[2:0] | b00000 | b01;
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}
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C.SLLI64 {//(RV128 RV32/64)
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encoding:b000 | b0 | rs1[4:0] | b00000 | b10;
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}
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C.LDSP {//(RV64/128
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encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
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args_disass: "x%rd$d, sp, 0x%imm$05x";
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}
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C.SDSP {//(RV64/128)
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encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
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}
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}
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}
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InsructionSet RV128IC extends RV64IC {
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constants {
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XLEN
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}
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address_spaces {
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MEM[8]
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}
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registers {
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[31:0] X[XLEN],
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PC[XLEN](is_pc)
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}
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instructions{
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C.LQ { //(RV128)
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encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
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}
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C.SQ { //(RV128)
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encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
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}
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C.SQSP {//(RV128)
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encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
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}
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}
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}
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