318 lines
12 KiB
C++
318 lines
12 KiB
C++
/*
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* riscv_target_adapter.h
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*
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* Created on: 26.09.2017
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* Author: eyck
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*/
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#ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
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#include "iss/arch_if.h"
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#include <iss/arch/traits.h>
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#include <iss/debugger/target_adapter_base.h>
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#include <iss/iss.h>
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#include <memory>
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#include <util/logging.h>
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namespace iss {
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namespace debugger {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> struct riscv_target_adapter : public target_adapter_base {
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riscv_target_adapter(server_if *srv, iss::arch_if *core)
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: target_adapter_base(srv)
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, core(core) {}
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/*============== Thread Control ===============================*/
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/* Set generic thread */
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status set_gen_thread(rp_thread_ref &thread) override;
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/* Set control thread */
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status set_ctrl_thread(rp_thread_ref &thread) override;
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/* Get thread status */
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status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
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/*============= Register Access ================================*/
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/* Read all registers. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
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/* Write all registers. buf is 4-byte aligned and it is in target
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byte order */
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status write_registers(const std::vector<uint8_t> &data) override;
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/* Read one register. buf is 4-byte aligned and it is in
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target byte order. If register is not available
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corresponding bytes in avail_buf are 0, otherwise
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avail buf is 1 */
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status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
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std::vector<uint8_t> &avail_buf) override;
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/* Write one register. buf is 4-byte aligned and it is in target byte
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order */
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status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
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/*=================== Memory Access =====================*/
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/* Read memory, buf is 4-bytes aligned and it is in target
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byte order */
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status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
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/* Write memory, buf is 4-bytes aligned and it is in target
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byte order */
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status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
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status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
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status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
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size_t &num, bool &done) override;
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status current_thread_query(rp_thread_ref &thread) override;
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status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
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status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
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status raw_query(std::string in_buf, std::string &out_buf) override;
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status threadinfo_query(int first, std::string &out_buf) override;
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status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
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status packetsize_query(std::string &out_buf) override;
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status add_break(int type, uint64_t addr, unsigned int length) override;
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status remove_break(int type, uint64_t addr, unsigned int length) override;
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status resume_from_addr(bool step, int sig, uint64_t addr) override;
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protected:
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static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
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iss::arch_if *core;
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rp_thread_ref thread_idx;
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};
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
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thread_idx = thread;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
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thread_idx = thread;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
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alive = 1;
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return Ok;
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}
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/* List threads. If first is non-zero then start from the first thread,
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* otherwise start from arg, result points to array of threads to be
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* filled out, result size is number of elements in the result,
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* num points to the actual number of threads found, done is
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* set if all threads are processed.
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*/
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
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std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
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bool &done) {
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if (first == 0) {
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result.clear();
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result.push_back(thread_idx);
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num = 1;
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done = true;
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return Ok;
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} else
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return NotSupported;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
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thread = thread_idx;
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return Ok;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
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LOG(TRACE) << "reading target registers";
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// return idx<0?:;
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data.clear();
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avail.clear();
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const uint8_t *reg_base = core->get_regs_base_ptr();
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for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
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auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
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unsigned offset = traits<ARCH>::reg_byte_offset(reg_no);
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for (size_t j = 0; j < reg_width; ++j) {
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data.push_back(*(reg_base + offset + j));
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avail.push_back(0xff);
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}
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}
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// work around fill with F type registers
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if (arch::traits<ARCH>::NUM_REGS < 65) {
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auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
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for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
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for (size_t j = 0; j < reg_width; ++j) {
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data.push_back(0x0);
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avail.push_back(0x00);
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}
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}
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}
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
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auto reg_count = arch::traits<ARCH>::NUM_REGS;
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auto *reg_base = core->get_regs_base_ptr();
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auto iter = data.data();
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for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
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auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
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auto offset = traits<ARCH>::reg_byte_offset(reg_no);
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std::copy(iter, iter + reg_width, reg_base);
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iter += 4;
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reg_base += offset;
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}
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return Ok;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
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std::vector<uint8_t> &avail) {
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if (reg_no < 65) {
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// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
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// arch::traits<ARCH>::reg_e>(reg_no))/8;
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auto *reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
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data.resize(reg_width);
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avail.resize(reg_width);
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auto offset = traits<ARCH>::reg_byte_offset(reg_no);
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std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
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std::fill(avail.begin(), avail.end(), 0xff);
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} else {
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typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
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data.resize(sizeof(typename traits<ARCH>::reg_t));
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avail.resize(sizeof(typename traits<ARCH>::reg_t));
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std::fill(avail.begin(), avail.end(), 0xff);
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core->read(a, data.size(), data.data());
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}
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return data.size() > 0 ? Ok : Err;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
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if (reg_no < 65) {
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auto *reg_base = core->get_regs_base_ptr();
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auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
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auto offset = traits<ARCH>::reg_byte_offset(reg_no);
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std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
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} else {
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typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
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core->write(a, data.size(), data.data());
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}
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
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auto a = map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
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auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
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return srv->execute_syncronized(f);
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
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auto a = map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
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return srv->execute_syncronized(&arch_if::write, core, a, data.size(), data.data());
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
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return NotSupported;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
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text = 0;
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data = 0;
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bss = 0;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
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return NotSupported;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
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return NotSupported;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
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if (first) {
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std::stringstream ss;
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ss << "m" << std::hex << thread_idx.val;
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out_buf = ss.str();
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} else {
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out_buf = "l";
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}
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return Ok;
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}
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template <typename ARCH>
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status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
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char buf[20];
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memset(buf, 0, 20);
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sprintf(buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
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out_buf = buf;
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
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out_buf = "PacketSize=1000";
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
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auto saddr = map_addr({iss::CODE, iss::PHYSICAL, addr});
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auto eaddr = map_addr({iss::CODE, iss::PHYSICAL, addr + length});
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target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
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LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
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<< saddr.val << std::dec;
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
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auto saddr = map_addr({iss::CODE, iss::PHYSICAL, addr});
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unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
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// TODO: check length of addr range
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if (handle) {
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LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
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<< std::dec;
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target_adapter_base::bp_lut.removeEntry(handle);
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Ok;
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}
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LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
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return Err;
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}
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template <typename ARCH> status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
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unsigned reg_no = arch::traits<ARCH>::PC;
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std::vector<uint8_t> data(8);
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*(reinterpret_cast<uint64_t *>(&data[0])) = addr;
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core->set_reg(reg_no, data);
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return resume_from_current(step, sig);
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}
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}
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}
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#endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */
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