358 lines
16 KiB
Plaintext
358 lines
16 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2020-2024 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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// clang-format off
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/tcc/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace tcc {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::tcc::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using mem_type_e = typename traits::mem_type_e;
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using addr_t = typename super::addr_t;
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using tu_builder = typename super::tu_builder;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = std::tuple<continuation_e>;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%
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if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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void add_prologue(tu_builder& tu) override;
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<%}%>
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void setup_module(std::string m) override {
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super::setup_module(m);
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}
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compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
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void gen_trap_behavior(tu_builder& tu) override;
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void gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(tu_builder& tu, unsigned lvl);
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inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
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inline void gen_set_tval(tu_builder& tu, value new_tval);
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inline void gen_trap_check(tu_builder& tu) {
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tu("if(*trap_state!=0) goto trap_entry;");
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}
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inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
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switch(reg_num){
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case traits::NEXT_PC:
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tu("*next_pc = {:#x};", pc.val);
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break;
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case traits::PC:
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tu("*pc = {:#x};", pc.val);
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break;
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default:
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if(!tu.defined_regs[reg_num]){
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tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
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tu.defined_regs[reg_num]=true;
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}
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tu("*reg{:02d} = {:#x};", reg_num, pc.val);
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}
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}
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct instruction_descriptor {
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uint32_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
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{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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//needs to be declared after instr_descr
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decoder instr_decoder;
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
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tu("${instr.name}_{:#010x}:", pc.val);
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vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
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uint64_t PC = pc.val;
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
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}
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auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
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pc=pc+ ${instr.length/8};
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gen_set_pc(tu, pc, traits::NEXT_PC);
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tu.open_scope();
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this->gen_set_tval(tu, instr);
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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tu.close_scope();
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vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
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gen_trap_check(tu);
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return returnValue;
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_instruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
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vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
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if(this->disass_enabled){
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/* generate console output when executing the command */
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tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
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}
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
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this->gen_set_tval(tu, instr);
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vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
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vm_impl::gen_trap_check(tu);
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return BRANCH;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
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volatile CODE_WORD x = instr;
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instr = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id)
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, instr_decoder([this]() {
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std::vector<generic_instruction_descriptor> g_instr_descr;
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g_instr_descr.reserve(instr_descr.size());
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for (uint32_t i = 0; i < instr_descr.size(); ++i) {
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generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
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g_instr_descr.push_back(new_instr_descr);
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}
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return std::move(g_instr_descr);
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}()) {}
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template <typename ARCH>
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std::tuple<continuation_e>
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vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
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// we fetch at max 4 byte, alignment is 2
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enum {TRAP_ID=1<<16};
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code_word_t instr = 0;
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phys_addr_t paddr(pc);
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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//TODO: re-add page handling
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// auto res = this->core.read(paddr, 2, data);
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// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
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// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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// }
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// } else {
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auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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// }
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if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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++inst_cnt;
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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compile_func f = nullptr;
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if(inst_index < instr_descr.size())
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f = instr_descr[inst_index].op;
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if (f == nullptr) {
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f = &this_class::illegal_instruction;
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}
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return (this->*f)(pc, instr, tu);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
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tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
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tu("leave_trap(core_ptr, {});", lvl);
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tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
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tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
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tu(fmt::format("tval = {};", new_tval));
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, value new_tval) {
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tu(fmt::format("tval = {};", new_tval.str));
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}
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template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
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tu("trap_entry:");
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this->gen_sync(tu, POST_SYNC, -1);
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tu("enter_trap(core_ptr, *trap_state, *pc, tval);");
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tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
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tu("return *next_pc;");
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}
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<%
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if(fcsr != null) {%>
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template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
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std::ostringstream os;
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os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
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os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
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os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
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os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
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os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
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os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
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os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
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os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
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os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
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os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
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os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
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os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
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os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
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os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
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os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
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os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
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os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
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os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
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os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
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os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
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os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
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os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
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os << "uint64_t (*fclass_d)(uint64_t v1 )=" << (uintptr_t)&fclass_d << ";\\n";
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os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
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os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
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os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
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tu.add_prologue(os.str());
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}
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<%}%>
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} // namespace ${coreDef.name.toLowerCase()}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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} // namesapce tcc
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} // namespace iss
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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#include <iss/factory.h>
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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}),
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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})
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};
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}
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}
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// clang-format on |