347 lines
15 KiB
Plaintext
347 lines
15 KiB
Plaintext
/*******************************************************************************
|
|
* Copyright (C) 2021 MINRES Technologies GmbH
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
*
|
|
* 1. Redistributions of source code must retain the above copyright notice,
|
|
* this list of conditions and the following disclaimer.
|
|
*
|
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
* and/or other materials provided with the distribution.
|
|
*
|
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
|
* may be used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
*******************************************************************************/
|
|
|
|
#include "../fp_functions.h"
|
|
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
|
#include <iss/arch/riscv_hart_m_p.h>
|
|
#include <iss/debugger/gdb_session.h>
|
|
#include <iss/debugger/server.h>
|
|
#include <iss/iss.h>
|
|
#include <iss/interp/vm_base.h>
|
|
#include <util/logging.h>
|
|
#include <sstream>
|
|
|
|
#ifndef FMT_HEADER_ONLY
|
|
#define FMT_HEADER_ONLY
|
|
#endif
|
|
#include <fmt/format.h>
|
|
|
|
#include <array>
|
|
#include <iss/debugger/riscv_target_adapter.h>
|
|
|
|
namespace iss {
|
|
namespace interp {
|
|
namespace ${coreDef.name.toLowerCase()} {
|
|
using namespace iss::arch;
|
|
using namespace iss::debugger;
|
|
|
|
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
|
|
public:
|
|
using traits = arch::traits<ARCH>;
|
|
using super = typename iss::interp::vm_base<ARCH>;
|
|
using virt_addr_t = typename super::virt_addr_t;
|
|
using phys_addr_t = typename super::phys_addr_t;
|
|
using code_word_t = typename super::code_word_t;
|
|
using addr_t = typename super::addr_t;
|
|
using reg_t = typename traits::reg_t;
|
|
using mem_type_e = typename traits::mem_type_e;
|
|
|
|
const bool has_compressed = traits::MISA_VAL & 0b100;
|
|
|
|
vm_impl();
|
|
|
|
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
|
|
|
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
|
|
|
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
|
debugger_if::dbg_enabled = true;
|
|
if (super::tgt_adapter == nullptr)
|
|
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
|
return super::tgt_adapter;
|
|
}
|
|
|
|
protected:
|
|
using this_class = vm_impl<ARCH>;
|
|
using compile_ret_t = virt_addr_t;
|
|
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
|
|
|
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
|
|
|
compile_func decode_inst(code_word_t instr) ;
|
|
virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
|
|
|
|
// some compile time constants
|
|
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
|
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
|
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
|
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
|
|
|
std::array<compile_func, LUT_SIZE> lut;
|
|
|
|
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
|
std::array<compile_func, LUT_SIZE> lut_11;
|
|
|
|
struct instruction_pattern {
|
|
uint32_t value;
|
|
uint32_t mask;
|
|
compile_func opc;
|
|
};
|
|
|
|
std::array<std::vector<instruction_pattern>, 4> qlut;
|
|
|
|
inline void raise(uint16_t trap_id, uint16_t cause){
|
|
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
|
|
this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
|
|
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
|
|
}
|
|
|
|
inline void leave(unsigned lvl){
|
|
this->core.leave_trap(lvl);
|
|
}
|
|
|
|
inline void wait(unsigned type){
|
|
this->core.wait_until(type);
|
|
}
|
|
|
|
template<typename T>
|
|
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
|
|
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
|
|
auto ret = super::template read_mem<uint8_t>(space, addr);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
return ret;
|
|
}
|
|
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
|
|
auto ret = super::template read_mem<uint16_t>(space, addr);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
return ret;
|
|
}
|
|
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
|
|
auto ret = super::template read_mem<uint32_t>(space, addr);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
return ret;
|
|
}
|
|
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
|
|
auto ret = super::template read_mem<uint64_t>(space, addr);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
return ret;
|
|
}
|
|
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
|
|
super::write_mem(space, addr, data);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
}
|
|
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
|
|
super::write_mem(space, addr, data);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
}
|
|
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
|
|
super::write_mem(space, addr, data);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
}
|
|
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
|
|
super::write_mem(space, addr, data);
|
|
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
|
|
}
|
|
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
|
|
inline S sext(U from) {
|
|
auto mask = (1ULL<<W) - 1;
|
|
auto sign_mask = 1ULL<<(W-1);
|
|
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
|
|
}
|
|
|
|
private:
|
|
/****************************************************************************
|
|
* start opcode definitions
|
|
****************************************************************************/
|
|
struct InstructionDesriptor {
|
|
size_t length;
|
|
uint32_t value;
|
|
uint32_t mask;
|
|
compile_func op;
|
|
};
|
|
|
|
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
|
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
|
/* instruction ${instr.instruction.name} */
|
|
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
|
}};
|
|
|
|
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
|
/* instruction ${idx}: ${instr.name} */
|
|
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
|
|
// pre execution stuff
|
|
auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
*PC=*NEXT_PC;
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
*trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
|
|
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
|
|
<%instr.fields.eachLine{%>${it}
|
|
<%}%>if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
<%instr.disass.eachLine{%>${it}
|
|
<%}%>
|
|
}
|
|
// used registers<%instr.usedVariables.each{ k,v->
|
|
if(v.isArray) {%>
|
|
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
|
|
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
|
|
<%}}%>// calculate next pc value
|
|
*NEXT_PC = *PC + ${instr.length/8};
|
|
// execute instruction
|
|
try {
|
|
<%instr.behavior.eachLine{%>${it}
|
|
<%}%>} catch(...){}
|
|
// post execution stuff
|
|
if(!has_compressed && (*NEXT_PC&0x3)!=0) raise(0, 0);
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val, instr);
|
|
} else {
|
|
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
|
|
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
|
|
}
|
|
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
<%}%>
|
|
/****************************************************************************
|
|
* end opcode definitions
|
|
****************************************************************************/
|
|
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
|
|
this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
|
|
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
|
|
raise(0, 2);
|
|
// post execution stuff
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
|
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
|
// trap check
|
|
if(*trap_state!=0){
|
|
super::core.enter_trap(*trap_state, pc.val, instr);
|
|
}
|
|
pc.val=*NEXT_PC;
|
|
return pc;
|
|
}
|
|
|
|
static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
|
|
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
|
|
auto phys_pc = this->core.v2p(pc);
|
|
//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
|
// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
|
|
// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
|
|
// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
|
|
//} else {
|
|
if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
|
|
//}
|
|
return iss::Ok;
|
|
}
|
|
};
|
|
|
|
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
|
volatile CODE_WORD x = insn;
|
|
insn = 2 * x;
|
|
}
|
|
|
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
|
|
|
// according to
|
|
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
|
|
#ifdef __GCC__
|
|
constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
|
|
#elif __cplusplus < 201402L
|
|
constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
|
|
constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
|
|
#else
|
|
constexpr size_t bit_count(uint32_t u) {
|
|
size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
|
|
return ((uCount + (uCount >> 3)) & 030707070707) % 63;
|
|
}
|
|
#endif
|
|
|
|
template <typename ARCH>
|
|
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
|
: vm_base<ARCH>(core, core_id, cluster_id) {
|
|
for (auto instr : instr_descr) {
|
|
auto quadrant = instr.value & 0x3;
|
|
qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
|
|
}
|
|
for(auto& lut: qlut){
|
|
std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
|
|
return bit_count(a.mask) > bit_count(b.mask);
|
|
});
|
|
}
|
|
}
|
|
|
|
inline bool is_count_limit_enabled(finish_cond_e cond){
|
|
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
|
|
}
|
|
|
|
inline bool is_jump_to_self_enabled(finish_cond_e cond){
|
|
return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
|
|
}
|
|
|
|
template <typename ARCH>
|
|
typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
|
|
for(auto& e: qlut[instr&0x3]){
|
|
if(!((instr&e.mask) ^ e.value )) return e.opc;
|
|
}
|
|
return &this_class::illegal_intruction;
|
|
}
|
|
|
|
template <typename ARCH>
|
|
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
|
|
// we fetch at max 4 byte, alignment is 2
|
|
code_word_t insn = 0;
|
|
auto *const data = (uint8_t *)&insn;
|
|
auto pc=start;
|
|
while(!this->core.should_stop() &&
|
|
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
|
|
auto res = fetch_ins(pc, data);
|
|
if(res!=iss::Ok){
|
|
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
|
|
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
|
|
} else {
|
|
if (is_jump_to_self_enabled(cond) &&
|
|
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
|
auto f = decode_inst(insn);
|
|
auto old_pc = pc.val;
|
|
pc = (this->*f)(pc, insn);
|
|
}
|
|
}
|
|
return pc;
|
|
}
|
|
|
|
} // namespace mnrv32
|
|
|
|
template <>
|
|
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
|
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
return std::unique_ptr<vm_if>(ret);
|
|
}
|
|
} // namespace interp
|
|
} // namespace iss
|