371 lines
15 KiB
Plaintext
371 lines
15 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2017-2024 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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// clang-format off
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/asmjit/vm_base.h>
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#include <asmjit/asmjit.h>
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#include <util/logging.h>
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#include <iss/instruction_decoder.h>
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<%def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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#include <vm/fp_functions.h><%}%>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace asmjit {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace ::asmjit;
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::asmjit::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using mem_type_e = typename super::mem_type_e;
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using addr_t = typename super::addr_t;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using super::get_ptr_for;
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using super::get_reg_for;
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using super::get_reg_for_Gp;
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using super::load_reg_from_mem;
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using super::load_reg_from_mem_Gp;
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using super::write_reg_to_mem;
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using super::gen_read_mem;
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using super::gen_write_mem;
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using super::gen_leave;
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using super::gen_sync;
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using this_class = vm_impl<ARCH>;
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using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
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continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
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enum globals_e {TVAL = 0, GLOBALS_SIZE};
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void gen_block_prologue(jit_holder& jh) override;
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void gen_block_epilogue(jit_holder& jh) override;
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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<%if(fcsr != null) {%>
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inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
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<%}%>
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void gen_instr_prologue(jit_holder& jh);
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void gen_instr_epilogue(jit_holder& jh);
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inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
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template <typename T, typename = typename std::enable_if<std::is_integral<T>::value>::type> void gen_set_tval(jit_holder& jh, T new_tval) ;
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void gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) ;
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct instruction_descriptor {
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uint32_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
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{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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//needs to be declared after instr_descr
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decoder instr_decoder;
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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continuation_e __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, jit_holder& jh){
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uint64_t PC = pc.val;
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate disass */
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<%instr.disass.eachLine{%>
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${it}<%}%>
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InvokeNode* call_print_disass;
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char* mnemonic_ptr = strdup(mnemonic.c_str());
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jh.disass_collection.push_back(mnemonic_ptr);
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jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
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call_print_disass->setArg(0, jh.arch_if_ptr);
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call_print_disass->setArg(1, pc.val);
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call_print_disass->setArg(2, mnemonic_ptr);
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}
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x86::Compiler& cc = jh.cc;
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cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
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gen_sync(jh, PRE_SYNC, ${idx});
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mov(cc, jh.pc, pc.val);
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gen_set_tval(jh, instr);
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pc = pc+${instr.length/8};
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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/*generate behavior*/
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<%instr.behavior.eachLine{%>${it}
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<%}%>
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gen_sync(jh, POST_SYNC, ${idx});
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gen_instr_epilogue(jh);
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return returnValue;
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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continuation_e illegal_instruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
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x86::Compiler& cc = jh.cc;
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if(this->disass_enabled){
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auto mnemonic = std::string("illegal_instruction");
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InvokeNode* call_print_disass;
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char* mnemonic_ptr = strdup(mnemonic.c_str());
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jh.disass_collection.push_back(mnemonic_ptr);
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jh.cc.invoke(&call_print_disass, &print_disass, FuncSignature::build<void, void *, uint64_t, char *>());
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call_print_disass->setArg(0, jh.arch_if_ptr);
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call_print_disass->setArg(1, pc.val);
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call_print_disass->setArg(2, mnemonic_ptr);
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}
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cc.comment(fmt::format("illegal_instruction{:#x}:",pc.val).c_str());
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gen_sync(jh, PRE_SYNC, instr_descr.size());
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mov(cc, jh.pc, pc.val);
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gen_set_tval(jh, instr);
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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mov(cc, jh.next_pc, pc.val);
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gen_instr_prologue(jh);
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cc.comment("//behavior:");
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gen_raise(jh, 0, 2);
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gen_sync(jh, POST_SYNC, instr_descr.size());
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gen_instr_epilogue(jh);
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return ILLEGAL_INSTR;
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}
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};
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id)
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, instr_decoder([this]() {
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std::vector<generic_instruction_descriptor> g_instr_descr;
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g_instr_descr.reserve(instr_descr.size());
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for (uint32_t i = 0; i < instr_descr.size(); ++i) {
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generic_instruction_descriptor new_instr_descr {instr_descr[i].value, instr_descr[i].mask, i};
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g_instr_descr.push_back(new_instr_descr);
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}
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return std::move(g_instr_descr);
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}()) {}
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template <typename ARCH>
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continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
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enum {TRAP_ID=1<<16};
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code_word_t instr = 0;
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phys_addr_t paddr(pc);
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auto *const data = (uint8_t *)&instr;
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if(this->core.has_mmu())
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paddr = this->core.virt2phys(pc);
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok)
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return ILLEGAL_FETCH;
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if (instr == 0x0000006f || (instr&0xffff)==0xa001)
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return JUMP_TO_SELF;
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++inst_cnt;
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uint32_t inst_index = instr_decoder.decode_instr(instr);
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compile_func f = nullptr;
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if(inst_index < instr_descr.size())
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f = instr_descr[inst_index].op;
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if (f == nullptr)
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f = &this_class::illegal_instruction;
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return (this->*f)(pc, instr, jh);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//gen_instr_prologue");
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x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
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auto& cc = jh.cc;
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cc.comment("//gen_instr_epilogue");
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x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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cmp(cc, current_trap_state, 0);
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cc.jne(jh.trap_entry);
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cc.inc(get_ptr_for(jh, traits::ICOUNT));
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cc.inc(get_ptr_for(jh, traits::CYCLE));
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
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jh.pc = load_reg_from_mem_Gp(jh, traits::PC);
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jh.next_pc = load_reg_from_mem_Gp(jh, traits::NEXT_PC);
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jh.globals.resize(GLOBALS_SIZE);
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jh.globals[TVAL] = get_reg_Gp(jh.cc, 64, false);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
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x86::Compiler& cc = jh.cc;
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cc.comment("//gen_block_epilogue");
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cc.ret(jh.next_pc);
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cc.bind(jh.trap_entry);
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this->write_back(jh);
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x86::Gp current_trap_state = get_reg_for_Gp(cc, traits::TRAP_STATE);
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mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
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x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
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mov(cc, current_pc, get_ptr_for(jh, traits::PC));
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cc.comment("//enter trap call;");
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InvokeNode* call_enter_trap;
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cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
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call_enter_trap->setArg(0, jh.arch_if_ptr);
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call_enter_trap->setArg(1, current_trap_state);
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call_enter_trap->setArg(2, current_pc);
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call_enter_trap->setArg(3, jh.globals[TVAL]);
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x86_reg_t current_next_pc = get_reg_for(cc, traits::NEXT_PC);
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mov(cc, current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
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mov(cc, jh.next_pc, current_next_pc);
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mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(UNKNOWN_JUMP));
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cc.ret(jh.next_pc);
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}
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template <typename ARCH>
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inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
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auto& cc = jh.cc;
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cc.comment("//gen_raise");
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auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
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mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
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mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
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cc.jmp(jh.trap_entry);
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}
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template <typename ARCH>
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template <typename T, typename>
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void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, T new_tval) {
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mov(jh.cc, jh.globals[TVAL], new_tval);
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}
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template <typename ARCH>
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void vm_impl<ARCH>::gen_set_tval(jit_holder& jh, x86_reg_t _new_tval) {
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if(nonstd::holds_alternative<x86::Gp>(_new_tval)) {
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x86::Gp new_tval = nonstd::get<x86::Gp>(_new_tval);
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if(new_tval.size() < 8)
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new_tval = gen_ext_Gp(jh.cc, new_tval, 64, false);
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mov(jh.cc, jh.globals[TVAL], new_tval);
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} else {
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throw std::runtime_error("Variant not supported in gen_set_tval");
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}
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}
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} // namespace tgc5c
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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} // namespace asmjit
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} // namespace iss
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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#include <iss/factory.h>
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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}),
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core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
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auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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})
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};
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}
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}
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// clang-format on |