354 lines
14 KiB
Plaintext
354 lines
14 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.util.BigIntegerWithRadix
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def nativeTypeSize(int size){
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if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
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}
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%>
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#include <vm/fp_functions.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/interp/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#include <boost/coroutine2/all.hpp>
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#include <functional>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace interp {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace iss::arch;
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using namespace iss::debugger;
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using namespace std::placeholders;
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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using opcode_e = typename traits::opcode_e;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (super::tgt_adapter == nullptr)
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super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return super::tgt_adapter;
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}
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protected:
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum {
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LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
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LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
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};
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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struct instruction_pattern {
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uint32_t value;
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uint32_t mask;
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typename arch::traits<ARCH>::opcode_e id;
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};
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std::array<std::vector<instruction_pattern>, 4> qlut;
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->core.trap_state = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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inline void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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}
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inline void wait(unsigned type){
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this->core.wait_until(type);
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}
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using yield_t = boost::coroutines2::coroutine<void>::push_type;
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using coro_t = boost::coroutines2::coroutine<void>::pull_type;
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std::vector<coro_t> spawn_blocks;
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template<typename T>
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T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint8_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint16_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint32_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
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auto ret = super::template read_mem<uint64_t>(space, addr);
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if(this->core.trap_state) throw 0;
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return ret;
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}
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inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
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super::write_mem(space, addr, data);
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if(this->core.trap_state) throw 0;
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}
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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inline void process_spawn_blocks() {
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for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
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if(*it){
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(*it)();
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++it;
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} else
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spawn_blocks.erase(it);
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}
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<%functions.each{ it.eachLine { %>
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${it}<%}%>
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<%}%>
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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typename arch::traits<ARCH>::opcode_e op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
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}};
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//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
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iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
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auto phys_pc = this->core.v2p(pc);
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//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
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// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
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// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
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//} else {
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if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
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//}
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return iss::Ok;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
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volatile CODE_WORD x = insn;
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insn = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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// according to
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// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
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#ifdef __GCC__
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constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
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#elif __cplusplus < 201402L
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constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
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constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
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#else
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constexpr size_t bit_count(uint32_t u) {
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size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
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return ((uCount + (uCount >> 3)) & 030707070707) % 63;
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}
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#endif
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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unsigned id=0;
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for (auto instr : instr_descr) {
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auto quadrant = instr.value & 0x3;
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qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
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}
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for(auto& lut: qlut){
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std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
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return bit_count(a.mask) > bit_count(b.mask);
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});
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}
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}
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inline bool is_count_limit_enabled(finish_cond_e cond){
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return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
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}
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inline bool is_jump_to_self_enabled(finish_cond_e cond){
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return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
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}
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template <typename ARCH>
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typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
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for(auto& e: qlut[instr&0x3]){
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if(!((instr&e.mask) ^ e.value )) return e.id;
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}
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return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
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}
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template <typename ARCH>
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typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
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auto pc=start;
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auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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auto& trap_state = this->core.trap_state;
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auto& icount = this->core.icount;
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auto& cycle = this->core.cycle;
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auto& instret = this->core.instret;
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auto& instr = this->core.instruction;
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// we fetch at max 4 byte, alignment is 2
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auto *const data = reinterpret_cast<uint8_t*>(&instr);
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while(!this->core.should_stop() &&
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!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
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if(fetch_ins(pc, data)!=iss::Ok){
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this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
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pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
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} else {
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if (is_jump_to_self_enabled(cond) &&
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(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto inst_id = decode_inst_id(instr);
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// pre execution stuff
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if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
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switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
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case arch::traits<ARCH>::opcode_e::${instr.name}: {
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */<%instr.disass.eachLine{%>
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${it}<%}%>
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}
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
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<%}}%>// calculate next pc value
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*NEXT_PC = *PC + ${instr.length/8};
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// execute instruction<%instr.behavior.eachLine{%>
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${it}<%}%>
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TRAP_${instr.name}:break;
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}// @suppress("No break at end of case")<%}%>
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default: {
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*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
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raise(0, 2);
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}
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}
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// post execution stuff
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process_spawn_blocks();
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
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// trap check
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if(trap_state!=0){
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super::core.enter_trap(trap_state, pc.val, instr);
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} else {
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icount++;
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instret++;
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}
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cycle++;
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pc.val=*NEXT_PC;
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this->core.reg.PC = this->core.reg.NEXT_PC;
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this->core.trap_state = this->core.pending_trap;
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}
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}
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return pc;
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}
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}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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} // namespace interp
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} // namespace iss
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