51 lines
2.0 KiB
Tcl
51 lines
2.0 KiB
Tcl
#############################################################################
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#
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#############################################################################
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proc getScriptDirectory {} {
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set dispScriptFile [file normalize [info script]]
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set scriptFolder [file dirname $dispScriptFile]
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return $scriptFolder
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}
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set hardware /HARDWARE/HW/HW
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set scriptDir [getScriptDirectory]
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set top_design_name core_complex
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set encap_name sysc::tgfs::${top_design_name}
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set clocks clk_i
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set resets rst_i
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set model_prefix "i_"
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set model_postfix ""
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::pct::new_project
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::pct::open_library TLM2_PL
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::pct::clear_systemc_defines
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::pct::clear_systemc_include_path
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::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
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::pct::set_import_protocol_generation_flag false
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::pct::set_update_existing_encaps_flag true
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::pct::set_dynamic_port_arrays_flag true
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::pct::set_import_scml_properties_flag true
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::pct::set_import_encap_prop_as_extra_prop_flag true
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::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
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# Set Port Protocols correctly
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set block ${top_design_name}
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foreach clock ${clocks} {
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::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
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}
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foreach reset ${resets} {
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::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
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}
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#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
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# Set compile settings and look
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set block SYSTEM_LIBRARY:${top_design_name}
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::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
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::pct::set_background_color_rgb $block 255 255 255 255
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}()
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::pct::set_bounds i_${top_design_name} 200 300 100 400
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::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
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# export the result as component
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::pct::export_system_library ${top_design_name} ${top_design_name}.xml
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