97 lines
3.5 KiB
Plaintext
97 lines
3.5 KiB
Plaintext
import "RV32IBase.core_desc"
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InsructionSet RV32M extends RV32IBase {
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constants {
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MAXLEN:=128
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}
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instructions{
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MUL{
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res , XLEN);
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}
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}
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MULH {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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MULHSU {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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MULHU {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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DIV {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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if(X[rs2]!=0){
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val M1[XLEN] <= -1;
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val MMIN[XLEN] <= -1<<(XLEN-1);
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if(X[rs1]s==MMIN's)
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if(X[rs2]s==M1's)
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X[rd]<=MMIN;
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else
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X[rd] <= X[rs1]s / X[rs2]s;
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else
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X[rd] <= X[rs1]s / X[rs2]s;
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}else
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X[rd] <= -1;
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}
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}
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DIVU {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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if(X[rs2]!=0)
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X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32);
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else
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X[rd] <= -1;
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}
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}
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REM {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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if(X[rs2]!=0) {
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val M1[XLEN] <= -1;
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val MMIN[XLEN] <= -1<<(XLEN-1);
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if(X[rs1]s==MMIN's)
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if(X[rs2]s==M1's)
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X[rd] <= 0;
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else
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X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
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else
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X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
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} else
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X[rd] <= X[rs1];
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}
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}
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REMU {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
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args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
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if(rd != 0){
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if(X[rs2]!=0)
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X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32);
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else
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X[rd] <= X[rs1];
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}
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}
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}
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} |