3556 lines
144 KiB
C++
3556 lines
144 KiB
C++
/*******************************************************************************
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* Copyright (C) 2017, 2023 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <asmjit/asmjit.h>
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#include <iss/arch/tgc5c.h>
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#include <iss/asmjit/vm_base.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <util/logging.h>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace asmjit {
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namespace tgc5c {
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using namespace ::asmjit;
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::asmjit::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::asmjit::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using mem_type_e = typename super::mem_type_e;
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using addr_t = typename super::addr_t;
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vm_impl();
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vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if* accquire_target_adapter(server_if* srv) override {
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debugger_if::dbg_enabled = true;
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if(vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using this_class = vm_impl<ARCH>;
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using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
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continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int&, jit_holder&) override;
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inline const char* name(size_t index) { return traits::reg_aliases.at(index); }
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template <unsigned W, typename U, typename S = typename std::make_signed<U>::type> inline S sext(U from) {
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auto mask = (1ULL << W) - 1;
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auto sign_mask = 1ULL << (W - 1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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#include "helper_func.h"
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct instruction_descriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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struct decoding_tree_node {
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std::vector<instruction_descriptor> instrs;
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std::vector<decoding_tree_node*> children;
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uint32_t submask = std::numeric_limits<uint32_t>::max();
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uint32_t value;
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decoding_tree_node(uint32_t value)
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: value(value) {}
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};
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decoding_tree_node* root{nullptr};
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const std::array<instruction_descriptor, 87> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */
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/* instruction LUI, encoding '0b00000000000000000000000000110111' */
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{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
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/* instruction AUIPC, encoding '0b00000000000000000000000000010111' */
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{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
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/* instruction JAL, encoding '0b00000000000000000000000001101111' */
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{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
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/* instruction JALR, encoding '0b00000000000000000000000001100111' */
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{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
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/* instruction BEQ, encoding '0b00000000000000000000000001100011' */
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{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
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/* instruction BNE, encoding '0b00000000000000000001000001100011' */
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{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
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/* instruction BLT, encoding '0b00000000000000000100000001100011' */
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{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
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/* instruction BGE, encoding '0b00000000000000000101000001100011' */
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{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
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/* instruction BLTU, encoding '0b00000000000000000110000001100011' */
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{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
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/* instruction BGEU, encoding '0b00000000000000000111000001100011' */
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{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
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/* instruction LB, encoding '0b00000000000000000000000000000011' */
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{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
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/* instruction LH, encoding '0b00000000000000000001000000000011' */
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{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
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/* instruction LW, encoding '0b00000000000000000010000000000011' */
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{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
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/* instruction LBU, encoding '0b00000000000000000100000000000011' */
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{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
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/* instruction LHU, encoding '0b00000000000000000101000000000011' */
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{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
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/* instruction SB, encoding '0b00000000000000000000000000100011' */
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{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
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/* instruction SH, encoding '0b00000000000000000001000000100011' */
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{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
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/* instruction SW, encoding '0b00000000000000000010000000100011' */
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{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
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/* instruction ADDI, encoding '0b00000000000000000000000000010011' */
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{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
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/* instruction SLTI, encoding '0b00000000000000000010000000010011' */
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{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
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/* instruction SLTIU, encoding '0b00000000000000000011000000010011' */
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{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
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/* instruction XORI, encoding '0b00000000000000000100000000010011' */
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{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
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/* instruction ORI, encoding '0b00000000000000000110000000010011' */
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{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
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/* instruction ANDI, encoding '0b00000000000000000111000000010011' */
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{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
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/* instruction SLLI, encoding '0b00000000000000000001000000010011' */
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{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
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/* instruction SRLI, encoding '0b00000000000000000101000000010011' */
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{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
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/* instruction SRAI, encoding '0b01000000000000000101000000010011' */
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{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
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/* instruction ADD, encoding '0b00000000000000000000000000110011' */
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{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
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/* instruction SUB, encoding '0b01000000000000000000000000110011' */
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{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
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/* instruction SLL, encoding '0b00000000000000000001000000110011' */
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{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
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/* instruction SLT, encoding '0b00000000000000000010000000110011' */
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{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
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/* instruction SLTU, encoding '0b00000000000000000011000000110011' */
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{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
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/* instruction XOR, encoding '0b00000000000000000100000000110011' */
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{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
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/* instruction SRL, encoding '0b00000000000000000101000000110011' */
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{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
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/* instruction SRA, encoding '0b01000000000000000101000000110011' */
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{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
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/* instruction OR, encoding '0b00000000000000000110000000110011' */
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{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
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/* instruction AND, encoding '0b00000000000000000111000000110011' */
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{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
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/* instruction FENCE, encoding '0b00000000000000000000000000001111' */
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{32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, &this_class::__fence},
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/* instruction ECALL, encoding '0b00000000000000000000000001110011' */
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{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
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/* instruction EBREAK, encoding '0b00000000000100000000000001110011' */
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{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
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/* instruction MRET, encoding '0b00110000001000000000000001110011' */
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{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
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/* instruction WFI, encoding '0b00010000010100000000000001110011' */
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{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
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/* instruction CSRRW, encoding '0b00000000000000000001000001110011' */
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{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
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/* instruction CSRRS, encoding '0b00000000000000000010000001110011' */
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{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
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/* instruction CSRRC, encoding '0b00000000000000000011000001110011' */
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{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
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/* instruction CSRRWI, encoding '0b00000000000000000101000001110011' */
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{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
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/* instruction CSRRSI, encoding '0b00000000000000000110000001110011' */
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{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
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/* instruction CSRRCI, encoding '0b00000000000000000111000001110011' */
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{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
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/* instruction FENCE_I, encoding '0b00000000000000000001000000001111' */
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{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
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/* instruction MUL, encoding '0b00000010000000000000000000110011' */
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{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
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/* instruction MULH, encoding '0b00000010000000000001000000110011' */
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{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
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/* instruction MULHSU, encoding '0b00000010000000000010000000110011' */
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{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
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/* instruction MULHU, encoding '0b00000010000000000011000000110011' */
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{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
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/* instruction DIV, encoding '0b00000010000000000100000000110011' */
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{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
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/* instruction DIVU, encoding '0b00000010000000000101000000110011' */
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{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
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/* instruction REM, encoding '0b00000010000000000110000000110011' */
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{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
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/* instruction REMU, encoding '0b00000010000000000111000000110011' */
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{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
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/* instruction C__ADDI4SPN, encoding '0b0000000000000000' */
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{16, 0b0000000000000000, 0b1110000000000011, &this_class::__c__addi4spn},
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/* instruction C__LW, encoding '0b0100000000000000' */
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{16, 0b0100000000000000, 0b1110000000000011, &this_class::__c__lw},
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/* instruction C__SW, encoding '0b1100000000000000' */
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{16, 0b1100000000000000, 0b1110000000000011, &this_class::__c__sw},
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/* instruction C__ADDI, encoding '0b0000000000000001' */
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{16, 0b0000000000000001, 0b1110000000000011, &this_class::__c__addi},
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/* instruction C__NOP, encoding '0b0000000000000001' */
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{16, 0b0000000000000001, 0b1110111110000011, &this_class::__c__nop},
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/* instruction C__JAL, encoding '0b0010000000000001' */
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{16, 0b0010000000000001, 0b1110000000000011, &this_class::__c__jal},
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/* instruction C__LI, encoding '0b0100000000000001' */
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{16, 0b0100000000000001, 0b1110000000000011, &this_class::__c__li},
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/* instruction C__LUI, encoding '0b0110000000000001' */
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{16, 0b0110000000000001, 0b1110000000000011, &this_class::__c__lui},
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/* instruction C__ADDI16SP, encoding '0b0110000100000001' */
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{16, 0b0110000100000001, 0b1110111110000011, &this_class::__c__addi16sp},
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/* instruction __reserved_clui, encoding '0b0110000000000001' */
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{16, 0b0110000000000001, 0b1111000001111111, &this_class::____reserved_clui},
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/* instruction C__SRLI, encoding '0b1000000000000001' */
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{16, 0b1000000000000001, 0b1111110000000011, &this_class::__c__srli},
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/* instruction C__SRAI, encoding '0b1000010000000001' */
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{16, 0b1000010000000001, 0b1111110000000011, &this_class::__c__srai},
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/* instruction C__ANDI, encoding '0b1000100000000001' */
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{16, 0b1000100000000001, 0b1110110000000011, &this_class::__c__andi},
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/* instruction C__SUB, encoding '0b1000110000000001' */
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{16, 0b1000110000000001, 0b1111110001100011, &this_class::__c__sub},
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/* instruction C__XOR, encoding '0b1000110000100001' */
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{16, 0b1000110000100001, 0b1111110001100011, &this_class::__c__xor},
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/* instruction C__OR, encoding '0b1000110001000001' */
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{16, 0b1000110001000001, 0b1111110001100011, &this_class::__c__or},
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/* instruction C__AND, encoding '0b1000110001100001' */
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{16, 0b1000110001100001, 0b1111110001100011, &this_class::__c__and},
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/* instruction C__J, encoding '0b1010000000000001' */
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{16, 0b1010000000000001, 0b1110000000000011, &this_class::__c__j},
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/* instruction C__BEQZ, encoding '0b1100000000000001' */
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{16, 0b1100000000000001, 0b1110000000000011, &this_class::__c__beqz},
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/* instruction C__BNEZ, encoding '0b1110000000000001' */
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{16, 0b1110000000000001, 0b1110000000000011, &this_class::__c__bnez},
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/* instruction C__SLLI, encoding '0b0000000000000010' */
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{16, 0b0000000000000010, 0b1111000000000011, &this_class::__c__slli},
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/* instruction C__LWSP, encoding '0b0100000000000010' */
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{16, 0b0100000000000010, 0b1110000000000011, &this_class::__c__lwsp},
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/* instruction C__MV, encoding '0b1000000000000010' */
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{16, 0b1000000000000010, 0b1111000000000011, &this_class::__c__mv},
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/* instruction C__JR, encoding '0b1000000000000010' */
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{16, 0b1000000000000010, 0b1111000001111111, &this_class::__c__jr},
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/* instruction __reserved_cmv, encoding '0b1000000000000010' */
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{16, 0b1000000000000010, 0b1111111111111111, &this_class::____reserved_cmv},
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/* instruction C__ADD, encoding '0b1001000000000010' */
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{16, 0b1001000000000010, 0b1111000000000011, &this_class::__c__add},
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/* instruction C__JALR, encoding '0b1001000000000010' */
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{16, 0b1001000000000010, 0b1111000001111111, &this_class::__c__jalr},
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/* instruction C__EBREAK, encoding '0b1001000000000010' */
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{16, 0b1001000000000010, 0b1111111111111111, &this_class::__c__ebreak},
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/* instruction C__SWSP, encoding '0b1100000000000010' */
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{16, 0b1100000000000010, 0b1110000000000011, &this_class::__c__swsp},
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/* instruction DII, encoding '0b0000000000000000' */
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{16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
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}};
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/* instruction definitions */
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/* instruction 0: LUI */
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continuation_e __lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
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uint64_t PC = pc.val;
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uint8_t rd = ((bit_sub<7, 5>(instr)));
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uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
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if(this->disass_enabled) {
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/* generate disass */
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}
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x86::Compiler& cc = jh.cc;
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// ideally only do this if necessary (someone / plugin needs it)
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cc.mov(jh.pc, PC);
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cc.comment(fmt::format("\nLUI_{:#x}:", pc.val).c_str());
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this->gen_sync(jh, PRE_SYNC, 0);
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pc = pc + 4;
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gen_instr_prologue(jh, pc.val);
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cc.comment("\n//behavior:");
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/*generate behavior*/
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if(rd >= static_cast<uint32_t>(traits::RFS)) {
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gen_raise(jh, 0, 2);
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} else {
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if(rd != 0) {
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cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)((int32_t)imm));
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}
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}
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auto returnValue = CONT;
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gen_instr_epilogue(jh);
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this->gen_sync(jh, POST_SYNC, 0);
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return returnValue;
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}
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/* instruction 1: AUIPC */
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continuation_e __auipc(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
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uint64_t PC = pc.val;
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uint8_t rd = ((bit_sub<7, 5>(instr)));
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uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
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if(this->disass_enabled) {
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/* generate disass */
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}
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|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nAUIPC_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 1);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)(PC + (int32_t)imm));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 1);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 2: JAL */
|
|
continuation_e __jal(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint32_t imm =
|
|
((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nJAL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 2);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)(PC + 4));
|
|
}
|
|
auto PC_val_v = (uint32_t)(PC + (int32_t)sext<21>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 2);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 3: JALR */
|
|
continuation_e __jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nJALR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 3);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto addr_mask = (uint32_t)-2;
|
|
auto new_pc = gen_ext(jh,
|
|
(gen_operation(jh, band,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
gen_ext(jh, addr_mask, 64, false))),
|
|
32, true);
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, urem, new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT)), 0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{ gen_raise(jh, 0, 0); }
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)(PC + 4));
|
|
}
|
|
auto PC_val_v = new_pc;
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 3);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 4: BEQ */
|
|
continuation_e __beq(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBEQ_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 4);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 4);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 5: BNE */
|
|
continuation_e __bne(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBNE_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 5);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 5);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 6: BLT */
|
|
continuation_e __blt(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBLT_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 6);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, lt, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false)),
|
|
0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 6);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 7: BGE */
|
|
continuation_e __bge(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBGE_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 7);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, gte, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false)),
|
|
0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 7);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 8: BLTU */
|
|
continuation_e __bltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBLTU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 8);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 8);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 9: BGEU */
|
|
continuation_e __bgeu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nBGEU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 9);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
|
|
gen_raise(jh, 0, 0);
|
|
} else {
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 9);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 10: LB */
|
|
continuation_e __lb(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nLB_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 10);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto load_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 1), 8, false);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 10);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 11: LH */
|
|
continuation_e __lh(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nLH_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 11);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto load_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 2), 16, false);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 11);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 12: LW */
|
|
continuation_e __lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nLW_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 12);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto load_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 4), 32, false);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 12);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 13: LBU */
|
|
continuation_e __lbu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nLBU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 13);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto load_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
auto res = gen_read_mem(jh, traits::MEM, load_address, 1);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 13);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 14: LHU */
|
|
continuation_e __lhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nLHU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 14);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto load_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
auto res = gen_read_mem(jh, traits::MEM, load_address, 2);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 14);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 15: SB */
|
|
continuation_e __sb(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSB_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 15);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto store_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 8, false));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 15);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 16: SH */
|
|
continuation_e __sh(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSH_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 16);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto store_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 16, false));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 16);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 17: SW */
|
|
continuation_e __sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSW_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 17);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto store_address = gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true);
|
|
gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 17);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 18: ADDI */
|
|
continuation_e __addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nADDI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 18);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int16_t)sext<12>(imm), 64, true))),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 18);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 19: SLTI */
|
|
continuation_e __slti(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLTI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 19);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
{
|
|
auto label_then = cc.newLabel();
|
|
auto label_merge = cc.newLabel();
|
|
auto tmp_reg = get_reg_for(jh, 1);
|
|
cc.cmp(gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm));
|
|
cc.jl(label_then);
|
|
cc.mov(tmp_reg, 0);
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_then);
|
|
cc.mov(tmp_reg, 1);
|
|
cc.bind(label_merge);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, tmp_reg, 32, false));
|
|
}
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 19);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 20: SLTIU */
|
|
continuation_e __sltiu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLTIU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 20);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
{
|
|
auto label_then = cc.newLabel();
|
|
auto label_merge = cc.newLabel();
|
|
auto tmp_reg = get_reg_for(jh, 1);
|
|
cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)));
|
|
cc.jb(label_then);
|
|
cc.mov(tmp_reg, 0);
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_then);
|
|
cc.mov(tmp_reg, 1);
|
|
cc.bind(label_merge);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, tmp_reg, 32, false));
|
|
}
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 20);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 21: XORI */
|
|
continuation_e __xori(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nXORI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 21);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 21);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 22: ORI */
|
|
continuation_e __ori(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nORI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 22);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 22);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 23: ANDI */
|
|
continuation_e __andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nANDI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 23);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 23);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 24: SLLI */
|
|
continuation_e __slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLLI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 24);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 24);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 25: SRLI */
|
|
continuation_e __srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSRLI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 25);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 25);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 26: SRAI */
|
|
continuation_e __srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSRAI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 26);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, sar, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true),
|
|
gen_ext(jh, shamt, 32, false))),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 26);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 27: ADD */
|
|
continuation_e __add(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nADD_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 27);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))),
|
|
32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 27);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 28: SUB */
|
|
continuation_e __sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSUB_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 28);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, sub, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 28);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 29: SLL */
|
|
continuation_e __sll(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 29);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
gen_operation(jh, shl, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
(gen_operation(jh, band, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false),
|
|
(static_cast<uint32_t>(traits::XLEN) - 1)))),
|
|
32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 29);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 30: SLT */
|
|
continuation_e __slt(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLT_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 30);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
{
|
|
auto label_then = cc.newLabel();
|
|
auto label_merge = cc.newLabel();
|
|
auto tmp_reg = get_reg_for(jh, 1);
|
|
cc.cmp(gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true));
|
|
cc.jl(label_then);
|
|
cc.mov(tmp_reg, 0);
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_then);
|
|
cc.mov(tmp_reg, 1);
|
|
cc.bind(label_merge);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, tmp_reg, 32, false));
|
|
}
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 30);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 31: SLTU */
|
|
continuation_e __sltu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSLTU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 31);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
{
|
|
auto label_then = cc.newLabel();
|
|
auto label_merge = cc.newLabel();
|
|
auto tmp_reg = get_reg_for(jh, 1);
|
|
cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2));
|
|
cc.jb(label_then);
|
|
cc.mov(tmp_reg, 0);
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_then);
|
|
cc.mov(tmp_reg, 1);
|
|
cc.bind(label_merge);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, tmp_reg, 32, false));
|
|
}
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 31);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 32: XOR */
|
|
continuation_e __xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nXOR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 32);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 32);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 33: SRL */
|
|
continuation_e __srl(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSRL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 33);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
gen_operation(jh, shr, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
(gen_operation(jh, band, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false),
|
|
(static_cast<uint32_t>(traits::XLEN) - 1)))),
|
|
32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 33);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 34: SRA */
|
|
continuation_e __sra(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nSRA_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 34);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_ext(jh,
|
|
gen_operation(
|
|
jh, sar, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true),
|
|
(gen_operation(jh, band, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false),
|
|
(static_cast<uint32_t>(traits::XLEN) - 1)))),
|
|
32, true)),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 34);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 35: OR */
|
|
continuation_e __or(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nOR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 35);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 35);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 36: AND */
|
|
continuation_e __and(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nAND_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 36);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 36);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 37: FENCE */
|
|
continuation_e __fence(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t succ = ((bit_sub<20, 4>(instr)));
|
|
uint8_t pred = ((bit_sub<24, 4>(instr)));
|
|
uint8_t fm = ((bit_sub<28, 4>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nFENCE_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 37);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fence), (uint8_t)pred << 4 | succ);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 37);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 38: ECALL */
|
|
continuation_e __ecall(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nECALL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 38);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 11);
|
|
auto returnValue = TRAP;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 38);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 39: EBREAK */
|
|
continuation_e __ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nEBREAK_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 39);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 3);
|
|
auto returnValue = TRAP;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 39);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 40: MRET */
|
|
continuation_e __mret(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nMRET_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 40);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_leave(jh, 3);
|
|
auto returnValue = TRAP;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 40);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 41: WFI */
|
|
continuation_e __wfi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nWFI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 41);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_wait(jh, 1);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 41);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 42: CSRRW */
|
|
continuation_e __csrrw(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRW_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 42);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
|
|
if(rd != 0) {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
gen_write_mem(jh, traits::CSR, csr, xrs1);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
} else {
|
|
gen_write_mem(jh, traits::CSR, csr, xrs1);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 42);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 43: CSRRS */
|
|
continuation_e __csrrs(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRS_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 43);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
|
|
if(rs1 != 0) {
|
|
gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, xrs1));
|
|
}
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 43);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 44: CSRRC */
|
|
continuation_e __csrrc(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRC_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 44);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
|
|
if(rs1 != 0) {
|
|
gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, gen_operation(jh, bnot, xrs1)));
|
|
}
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 44);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 45: CSRRWI */
|
|
continuation_e __csrrwi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRWI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 45);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 45);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 46: CSRRSI */
|
|
continuation_e __csrrsi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRSI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 46);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
if(zimm != 0) {
|
|
gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, (uint32_t)zimm));
|
|
}
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 46);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 47: CSRRCI */
|
|
continuation_e __csrrci(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15, 5>(instr)));
|
|
uint16_t csr = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nCSRRCI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 47);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
|
|
if(zimm != 0) {
|
|
gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, ~((uint32_t)zimm)));
|
|
}
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), xrd);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 47);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 48: FENCE_I */
|
|
continuation_e __fence_i(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint16_t imm = ((bit_sub<20, 12>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nFENCE_I_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 48);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fencei), imm);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 48);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 49: MUL */
|
|
continuation_e __mul(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nMUL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 49);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto res = gen_ext(
|
|
jh,
|
|
(gen_operation(
|
|
jh, imul, gen_ext(jh, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true),
|
|
gen_ext(jh, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true))),
|
|
64, true);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, res, 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 49);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 50: MULH */
|
|
continuation_e __mulh(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nMULH_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 50);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto res = gen_ext(
|
|
jh,
|
|
(gen_operation(
|
|
jh, imul, gen_ext(jh, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true),
|
|
gen_ext(jh, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true))),
|
|
64, true);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh, (gen_operation(jh, sar, res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))), 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 50);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 51: MULHSU */
|
|
continuation_e __mulhsu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nMULHSU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 51);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto res = gen_ext(
|
|
jh,
|
|
(gen_operation(
|
|
jh, imul, gen_ext(jh, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true),
|
|
gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false))),
|
|
64, true);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh, (gen_operation(jh, sar, res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))), 32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 51);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 52: MULHU */
|
|
continuation_e __mulhu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nMULHU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 52);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto res =
|
|
gen_ext(jh,
|
|
(gen_operation(jh, mul, gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), 128, false),
|
|
gen_ext(jh, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false))),
|
|
64, false);
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh, (gen_operation(jh, shr, res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))), 32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 52);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 53: DIV */
|
|
continuation_e __div(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nDIV_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 53);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto dividend = gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, false);
|
|
auto divisor = gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false);
|
|
if(rd != 0) {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, divisor, gen_ext(jh, 0, 32, false)), 0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{
|
|
auto MMIN = ((uint32_t)1) << (static_cast<uint32_t>(traits::XLEN) - 1);
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN),
|
|
gen_operation(jh, eq, divisor, gen_ext(jh, -1, 32, true))),
|
|
0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{ cc.mov(get_reg_ptr(jh, traits::X0 + rd), MMIN); }
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh, (gen_operation(jh, idiv, gen_ext(jh, dividend, 64, true), gen_ext(jh, divisor, 64, true))), 32,
|
|
true));
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{ cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)-1); }
|
|
cc.bind(label_merge);
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 53);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 54: DIVU */
|
|
continuation_e __divu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nDIVU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 54);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)), 0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh,
|
|
(gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1),
|
|
load_reg_from_mem(jh, traits::X0 + rs2))),
|
|
32, false));
|
|
}
|
|
}
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)-1);
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 54);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 55: REM */
|
|
continuation_e __rem(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nREM_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 55);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)), 0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{
|
|
auto MMIN = (uint32_t)1 << (static_cast<uint32_t>(traits::XLEN) - 1);
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN),
|
|
gen_operation(jh, eq, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false),
|
|
gen_ext(jh, -1, 32, true))),
|
|
0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, 0, 32, false));
|
|
}
|
|
}
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, srem, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false))),
|
|
32, true));
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs1));
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 55);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 56: REMU */
|
|
continuation_e __remu(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15, 5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nREMU_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 56);
|
|
pc = pc + 4;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
|
|
rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)), 0);
|
|
auto label_else = cc.newLabel();
|
|
cc.je(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)));
|
|
}
|
|
}
|
|
cc.jmp(label_merge);
|
|
cc.bind(label_else);
|
|
{
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs1));
|
|
}
|
|
}
|
|
cc.bind(label_merge);
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 56);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 57: C__ADDI4SPN */
|
|
continuation_e __c__addi4spn(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<2, 3>(instr)));
|
|
uint16_t imm =
|
|
((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__ADDI4SPN_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 57);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(imm) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8),
|
|
gen_ext(
|
|
jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, imm, 64, false))),
|
|
32, false));
|
|
} else {
|
|
gen_raise(jh, 0, 2);
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 57);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 58: C__LW */
|
|
continuation_e __c__lw(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<2, 3>(instr)));
|
|
uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__LW_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 58);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto offs = gen_ext(
|
|
jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1 + 8), 64, false), gen_ext(jh, uimm, 64, false))),
|
|
32, false);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8), gen_ext(jh, gen_ext(jh, gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 58);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 59: C__SW */
|
|
continuation_e __c__sw(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 3>(instr)));
|
|
uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SW_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 59);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto offs = gen_ext(
|
|
jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1 + 8), 64, false), gen_ext(jh, uimm, 64, false))),
|
|
32, false);
|
|
gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2 + 8), 32, false));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 59);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 60: C__ADDI */
|
|
continuation_e __c__addi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__ADDI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 60);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rs1 != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false),
|
|
gen_ext(jh, (int8_t)sext<6>(imm), 64, true))),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 60);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 61: C__NOP */
|
|
continuation_e __c__nop(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__NOP_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 61);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 61);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 62: C__JAL */
|
|
continuation_e __c__jal(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
|
|
(bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__JAL_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 62);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + 1), (uint32_t)(PC + 2));
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 62);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 63: C__LI */
|
|
continuation_e __c__li(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__LI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 63);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)((int8_t)sext<6>(imm)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 63);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 64: C__LUI */
|
|
continuation_e __c__lui(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17));
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__LUI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 64);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(imm == 0 || rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
}
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), (uint32_t)((int32_t)sext<18>(imm)));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 64);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 65: C__ADDI16SP */
|
|
continuation_e __c__addi16sp(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) |
|
|
(bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__ADDI16SP_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 65);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(nzimm) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + 2),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false),
|
|
gen_ext(jh, (int16_t)sext<10>(nzimm), 64, true))),
|
|
32, true));
|
|
} else {
|
|
gen_raise(jh, 0, 2);
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 65);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 66: __reserved_clui */
|
|
continuation_e ____reserved_clui(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\n__reserved_clui_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 66);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 2);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 66);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 67: C__SRLI */
|
|
continuation_e __c__srli(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t shamt = ((bit_sub<2, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SRLI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 67);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1 + 8),
|
|
gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1 + 8), gen_ext(jh, shamt, 32, false)));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 67);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 68: C__SRAI */
|
|
continuation_e __c__srai(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t shamt = ((bit_sub<2, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SRAI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 68);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(shamt) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1 + 8),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, sar, (gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1 + 8), 32, false)),
|
|
gen_ext(jh, shamt, 32, false))),
|
|
32, true));
|
|
} else {
|
|
if(static_cast<uint32_t>(traits::XLEN) == 128) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1 + 8),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, sar, (gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1 + 8), 32, false)),
|
|
gen_ext(jh, 64, 32, false))),
|
|
32, true));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 68);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 69: C__ANDI */
|
|
continuation_e __c__andi(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__ANDI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 69);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1 + 8),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1 + 8), gen_ext(jh, (int8_t)sext<6>(imm), 32, true))),
|
|
32, true));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 69);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 70: C__SUB */
|
|
continuation_e __c__sub(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 3>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SUB_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 70);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, sub, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd + 8), 64, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2 + 8), 64, false))),
|
|
32, true));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 70);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 71: C__XOR */
|
|
continuation_e __c__xor(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 3>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__XOR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 71);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8),
|
|
gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd + 8), load_reg_from_mem(jh, traits::X0 + rs2 + 8)));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 71);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 72: C__OR */
|
|
continuation_e __c__or(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 3>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__OR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 72);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8),
|
|
gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd + 8), load_reg_from_mem(jh, traits::X0 + rs2 + 8)));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 72);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 73: C__AND */
|
|
continuation_e __c__and(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 3>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__AND_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 73);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd + 8),
|
|
gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd + 8), load_reg_from_mem(jh, traits::X0 + rs2 + 8)));
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 73);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 74: C__J */
|
|
continuation_e __c__j(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm =
|
|
((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
|
|
(bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__J_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 74);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 74);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 75: C__BEQZ */
|
|
continuation_e __c__beqz(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
|
|
(bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__BEQZ_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 75);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1 + 8), gen_ext(jh, 0, 32, false)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
cc.bind(label_merge);
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 75);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 76: C__BNEZ */
|
|
continuation_e __c__bnez(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
|
|
(bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
|
|
uint8_t rs1 = ((bit_sub<7, 3>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__BNEZ_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 76);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
auto label_merge = cc.newLabel();
|
|
cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1 + 8), gen_ext(jh, 0, 32, false)), 0);
|
|
cc.je(label_merge);
|
|
{
|
|
auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
cc.bind(label_merge);
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 76);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 77: C__SLLI */
|
|
continuation_e __c__slli(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t nzuimm = ((bit_sub<2, 5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SLLI_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 77);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rs1 != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rs1),
|
|
gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, nzuimm, 32, false)));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 77);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 78: C__LWSP */
|
|
continuation_e __c__lwsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5));
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__LWSP_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 78);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS) || rd == 0) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto offs = gen_ext(
|
|
jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false))),
|
|
32, false);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), gen_ext(jh, gen_ext(jh, gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 78);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 79: C__MV */
|
|
continuation_e __c__mv(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 5>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__MV_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 79);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 79);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 80: C__JR */
|
|
continuation_e __c__jr(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs1 = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__JR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 80);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs1 && rs1 < static_cast<uint32_t>(traits::RFS)) {
|
|
auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1 % static_cast<uint32_t>(traits::RFS)),
|
|
gen_ext(jh, ~0x1, 32, false));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
} else {
|
|
gen_raise(jh, 0, 2);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 80);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 81: __reserved_cmv */
|
|
continuation_e ____reserved_cmv(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\n__reserved_cmv_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 81);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 2);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 81);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 82: C__ADD */
|
|
continuation_e __c__add(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 5>(instr)));
|
|
uint8_t rd = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__ADD_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 82);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rd >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
if(rd != 0) {
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + rd),
|
|
gen_ext(jh,
|
|
(gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd), 64, false),
|
|
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))),
|
|
32, false));
|
|
}
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 82);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 83: C__JALR */
|
|
continuation_e __c__jalr(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs1 = ((bit_sub<7, 5>(instr)));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__JALR_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 83);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1);
|
|
cc.mov(get_reg_ptr(jh, traits::X0 + 1), (uint32_t)(PC + 2));
|
|
auto PC_val_v = gen_operation(jh, band, new_pc, gen_ext(jh, ~0x1, 32, false));
|
|
cc.mov(jh.next_pc, PC_val_v);
|
|
cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
|
|
}
|
|
auto returnValue = BRANCH;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 83);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 84: C__EBREAK */
|
|
continuation_e __c__ebreak(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__EBREAK_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 84);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 3);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 84);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 85: C__SWSP */
|
|
continuation_e __c__swsp(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
uint8_t rs2 = ((bit_sub<2, 5>(instr)));
|
|
uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2));
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nC__SWSP_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 85);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
if(rs2 >= static_cast<uint32_t>(traits::RFS)) {
|
|
gen_raise(jh, 0, 2);
|
|
} else {
|
|
auto offs = gen_ext(
|
|
jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false))),
|
|
32, false);
|
|
gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false));
|
|
}
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 85);
|
|
return returnValue;
|
|
}
|
|
|
|
/* instruction 86: DII */
|
|
continuation_e __dii(virt_addr_t& pc, code_word_t instr, jit_holder& jh) {
|
|
uint64_t PC = pc.val;
|
|
if(this->disass_enabled) {
|
|
/* generate disass */
|
|
}
|
|
x86::Compiler& cc = jh.cc;
|
|
// ideally only do this if necessary (someone / plugin needs it)
|
|
cc.mov(jh.pc, PC);
|
|
cc.comment(fmt::format("\nDII_{:#x}:", pc.val).c_str());
|
|
this->gen_sync(jh, PRE_SYNC, 86);
|
|
pc = pc + 2;
|
|
|
|
gen_instr_prologue(jh, pc.val);
|
|
cc.comment("\n//behavior:");
|
|
/*generate behavior*/
|
|
gen_raise(jh, 0, 2);
|
|
auto returnValue = CONT;
|
|
|
|
gen_instr_epilogue(jh);
|
|
this->gen_sync(jh, POST_SYNC, 86);
|
|
return returnValue;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* end opcode definitions
|
|
****************************************************************************/
|
|
continuation_e illegal_intruction(virt_addr_t& pc, code_word_t instr, jit_holder& jh) { return BRANCH; }
|
|
// decoding functionality
|
|
|
|
void populate_decoding_tree(decoding_tree_node* root) {
|
|
// create submask
|
|
for(auto instr : root->instrs) {
|
|
root->submask &= instr.mask;
|
|
}
|
|
// put each instr according to submask&encoding into children
|
|
for(auto instr : root->instrs) {
|
|
bool foundMatch = false;
|
|
for(auto child : root->children) {
|
|
// use value as identifying trait
|
|
if(child->value == (instr.value & root->submask)) {
|
|
child->instrs.push_back(instr);
|
|
foundMatch = true;
|
|
}
|
|
}
|
|
if(!foundMatch) {
|
|
decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask);
|
|
child->instrs.push_back(instr);
|
|
root->children.push_back(child);
|
|
}
|
|
}
|
|
root->instrs.clear();
|
|
// call populate_decoding_tree for all children
|
|
if(root->children.size() > 1)
|
|
for(auto child : root->children) {
|
|
populate_decoding_tree(child);
|
|
}
|
|
else {
|
|
// sort instrs by value of the mask, this works bc we want to have the least restrictive one last
|
|
std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(),
|
|
[](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; });
|
|
}
|
|
}
|
|
compile_func decode_instr(decoding_tree_node* node, code_word_t word) {
|
|
if(!node->children.size()) {
|
|
if(node->instrs.size() == 1)
|
|
return node->instrs[0].op;
|
|
for(auto instr : node->instrs) {
|
|
if((instr.mask & word) == instr.value)
|
|
return instr.op;
|
|
}
|
|
} else {
|
|
for(auto child : node->children) {
|
|
if(child->value == (node->submask & word)) {
|
|
return decode_instr(child, word);
|
|
}
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
};
|
|
|
|
template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
|
|
volatile CODE_WORD x = instr;
|
|
instr = 2 * x;
|
|
}
|
|
|
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
|
|
|
template <typename ARCH>
|
|
vm_impl<ARCH>::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id)
|
|
: vm_base<ARCH>(core, core_id, cluster_id) {
|
|
root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
|
|
for(auto instr : instr_descr) {
|
|
root->instrs.push_back(instr);
|
|
}
|
|
populate_decoding_tree(root);
|
|
}
|
|
|
|
template <typename ARCH> continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, jit_holder& jh) {
|
|
enum { TRAP_ID = 1 << 16 };
|
|
code_word_t instr = 0;
|
|
phys_addr_t paddr(pc);
|
|
auto* const data = (uint8_t*)&instr;
|
|
if(this->core.has_mmu())
|
|
paddr = this->core.virt2phys(pc);
|
|
auto res = this->core.read(paddr, 4, data);
|
|
if(res != iss::Ok)
|
|
throw trap_access(TRAP_ID, pc.val);
|
|
if(instr == 0x0000006f || (instr & 0xffff) == 0xa001)
|
|
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
|
++inst_cnt;
|
|
auto f = decode_instr(root, instr);
|
|
if(f == nullptr)
|
|
f = &this_class::illegal_intruction;
|
|
return (this->*f)(pc, instr, jh);
|
|
}
|
|
|
|
} // namespace tgc5c
|
|
|
|
template <> std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c* core, unsigned short port, bool dump) {
|
|
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
|
|
if(port != 0)
|
|
debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
return std::unique_ptr<vm_if>(ret);
|
|
}
|
|
} // namespace asmjit
|
|
} // namespace iss
|
|
|
|
#include <iss/arch/riscv_hart_m_p.h>
|
|
#include <iss/arch/riscv_hart_mu_p.h>
|
|
#include <iss/factory.h>
|
|
namespace iss {
|
|
namespace {
|
|
volatile std::array<bool, 2> dummy = {
|
|
core_factory::instance().register_creator("tgc5c|m_p|asmjit",
|
|
[](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
|
|
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
|
|
auto* vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
|
if(port != 0)
|
|
debugger::server<debugger::gdb_session>::run_server(vm, port);
|
|
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
|
}),
|
|
core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
|
|
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
|
|
auto* vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
|
if(port != 0)
|
|
debugger::server<debugger::gdb_session>::run_server(vm, port);
|
|
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
|
})};
|
|
}
|
|
} // namespace iss
|