321 lines
8.8 KiB
C++
321 lines
8.8 KiB
C++
/*******************************************************************************
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* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef _TGC5C_H_
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#define _TGC5C_H_
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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namespace iss {
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namespace arch {
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struct tgc5c;
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template <> struct traits<tgc5c> {
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constexpr static char const* const core_type = "TGC5C";
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static constexpr std::array<const char*, 36> reg_names{{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8",
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"x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17",
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"x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26",
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"x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
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static constexpr std::array<const char*, 36> reg_aliases{
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{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
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enum constants {
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MISA_VAL = 1073746180ULL,
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MARCHID_VAL = 2147483651ULL,
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XLEN = 32ULL,
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INSTR_ALIGNMENT = 2ULL,
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RFS = 32ULL,
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fence = 0ULL,
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fencei = 1ULL,
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fencevmal = 2ULL,
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fencevmau = 3ULL,
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CSR_SIZE = 4096ULL,
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MUL_LEN = 64ULL
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};
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constexpr static unsigned FP_REGS_SIZE = 0;
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enum reg_e {
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X0,
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X1,
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X2,
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X3,
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X4,
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X5,
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X6,
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X7,
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X8,
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X9,
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X10,
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X11,
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X12,
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X13,
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X14,
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X15,
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X16,
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X17,
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X18,
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X19,
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X20,
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X21,
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X22,
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X23,
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X24,
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X25,
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X26,
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X27,
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X28,
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X29,
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X30,
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X31,
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PC,
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NEXT_PC,
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PRIV,
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DPC,
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NUM_REGS,
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TRAP_STATE = NUM_REGS,
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PENDING_TRAP,
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ICOUNT,
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CYCLE,
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INSTRET,
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INSTRUCTION,
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LAST_BRANCH
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};
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using reg_t = uint32_t;
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using addr_t = uint32_t;
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using code_word_t = uint32_t; // TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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static constexpr std::array<const uint32_t, 43> reg_bit_widths{{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 8, 32, 32, 32, 64, 64, 64, 32, 32}};
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static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
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{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84,
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88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 137, 141, 145, 149, 157, 165, 173, 177}};
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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enum mem_type_e { MEM, FENCE, RES, CSR };
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enum class opcode_e {
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LUI = 0,
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AUIPC = 1,
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JAL = 2,
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JALR = 3,
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BEQ = 4,
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BNE = 5,
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BLT = 6,
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BGE = 7,
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BLTU = 8,
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BGEU = 9,
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LB = 10,
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LH = 11,
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LW = 12,
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LBU = 13,
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LHU = 14,
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SB = 15,
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SH = 16,
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SW = 17,
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ADDI = 18,
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SLTI = 19,
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SLTIU = 20,
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XORI = 21,
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ORI = 22,
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ANDI = 23,
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SLLI = 24,
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SRLI = 25,
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SRAI = 26,
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ADD = 27,
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SUB = 28,
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SLL = 29,
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SLT = 30,
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SLTU = 31,
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XOR = 32,
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SRL = 33,
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SRA = 34,
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OR = 35,
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AND = 36,
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FENCE = 37,
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ECALL = 38,
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EBREAK = 39,
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MRET = 40,
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WFI = 41,
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CSRRW = 42,
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CSRRS = 43,
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CSRRC = 44,
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CSRRWI = 45,
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CSRRSI = 46,
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CSRRCI = 47,
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FENCE_I = 48,
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MUL = 49,
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MULH = 50,
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MULHSU = 51,
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MULHU = 52,
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DIV = 53,
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DIVU = 54,
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REM = 55,
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REMU = 56,
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C__ADDI4SPN = 57,
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C__LW = 58,
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C__SW = 59,
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C__ADDI = 60,
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C__NOP = 61,
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C__JAL = 62,
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C__LI = 63,
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C__LUI = 64,
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C__ADDI16SP = 65,
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__reserved_clui = 66,
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C__SRLI = 67,
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C__SRAI = 68,
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C__ANDI = 69,
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C__SUB = 70,
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C__XOR = 71,
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C__OR = 72,
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C__AND = 73,
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C__J = 74,
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C__BEQZ = 75,
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C__BNEZ = 76,
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C__SLLI = 77,
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C__LWSP = 78,
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C__MV = 79,
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C__JR = 80,
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__reserved_cmv = 81,
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C__ADD = 82,
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C__JALR = 83,
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C__EBREAK = 84,
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C__SWSP = 85,
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DII = 86,
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MAX_OPCODE
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};
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};
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struct tgc5c : public arch_if {
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using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
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using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
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using reg_t = typename traits<tgc5c>::reg_t;
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using addr_t = typename traits<tgc5c>::addr_t;
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tgc5c();
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~tgc5c();
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void reset(uint64_t address = 0) override;
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uint8_t* get_regs_base_ptr() override;
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inline uint64_t get_icount() { return reg.icount; }
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inline bool should_stop() { return interrupt_sim; }
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inline uint64_t stop_code() { return interrupt_sim; }
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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inline uint32_t get_last_branch() { return reg.last_branch; }
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#pragma pack(push, 1)
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struct TGC5C_regs {
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uint32_t X0 = 0;
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uint32_t X1 = 0;
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uint32_t X2 = 0;
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uint32_t X3 = 0;
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uint32_t X4 = 0;
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uint32_t X5 = 0;
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uint32_t X6 = 0;
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uint32_t X7 = 0;
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uint32_t X8 = 0;
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uint32_t X9 = 0;
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uint32_t X10 = 0;
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uint32_t X11 = 0;
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uint32_t X12 = 0;
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uint32_t X13 = 0;
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uint32_t X14 = 0;
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uint32_t X15 = 0;
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uint32_t X16 = 0;
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uint32_t X17 = 0;
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uint32_t X18 = 0;
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uint32_t X19 = 0;
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uint32_t X20 = 0;
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uint32_t X21 = 0;
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uint32_t X22 = 0;
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uint32_t X23 = 0;
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uint32_t X24 = 0;
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uint32_t X25 = 0;
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uint32_t X26 = 0;
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uint32_t X27 = 0;
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uint32_t X28 = 0;
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uint32_t X29 = 0;
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uint32_t X30 = 0;
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uint32_t X31 = 0;
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uint32_t PC = 0;
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uint32_t NEXT_PC = 0;
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uint8_t PRIV = 0;
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uint32_t DPC = 0;
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uint32_t trap_state = 0, pending_trap = 0;
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uint64_t icount = 0;
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uint64_t cycle = 0;
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uint64_t instret = 0;
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uint32_t instruction = 0;
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uint32_t last_branch = 0;
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} reg;
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#pragma pack(pop)
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std::array<address_type, 4> addr_mode;
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uint64_t interrupt_sim = 0;
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uint32_t get_fcsr() { return 0; }
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void set_fcsr(uint32_t val) {}
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};
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} // namespace arch
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} // namespace iss
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#endif /* _TGC5C_H_ */
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