180 lines
6.5 KiB
Plaintext
180 lines
6.5 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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def getTypeSize(size){
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if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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namespace iss {
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namespace arch {
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struct ${coreDef.name.toLowerCase()};
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template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static char const* const core_type = "${coreDef.name}";
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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${reg.name}${it},<%
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}
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} else if(reg instanceof Register){ %>
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${reg.name},<%
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}
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}%>
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NUM_REGS,
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NEXT_${pc.name}=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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LAST_BRANCH,
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ICOUNT
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};
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using reg_t = uint${regDataWidth}_t;
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using addr_t = uint${addrDataWidth}_t;
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using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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static constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{
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{${regSizes.join(",")}}};
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static constexpr unsigned reg_bit_width(unsigned r) { return ${coreDef.name}_reg_size[r]; }
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static constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{
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{${regOffsets.join(",")}}};
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constexpr static unsigned reg_byte_offset(unsigned r) { return ${coreDef.name}_reg_byte_offset[r]; }
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
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using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
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using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
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using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
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${coreDef.name.toLowerCase()}();
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~${coreDef.name.toLowerCase()}();
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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/// deprecated
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void get_reg(short idx, std::vector<uint8_t>& value) override {}
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void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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bool get_flag(int flag) override {return false;}
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void set_flag(int, bool value) override {};
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/// deprecated
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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inline uint64_t get_icount() { return reg.icount; }
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inline bool should_stop() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
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} else
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return virt2phys(addr);
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}
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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inline uint32_t get_last_branch() { return reg.last_branch; }
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protected:
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struct ${coreDef.name}_regs {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
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}
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} else if(reg instanceof Register){ %>
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uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
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}
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}%>
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uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
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uint64_t icount = 0;
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} reg;
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std::array<address_type, 4> addr_mode;
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bool interrupt_sim=false;
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<%
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def fcsr = allRegs.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
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void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
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<%} else { %>
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uint32_t get_fcsr(){return 0;}
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void set_fcsr(uint32_t val){}
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<%}%>
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};
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}
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}
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#endif /* _${coreDef.name.toUpperCase()}_H_ */
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