638 lines
26 KiB
C++
638 lines
26 KiB
C++
/*******************************************************************************
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* Copyright (C) 2020 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/arch/mnrv32.h>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/tcc/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace tcc {
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namespace mnrv32 {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
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public:
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using super = typename iss::tcc::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using Value = void;
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using ConstantInt = void;
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using Type = void;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm_base<ARCH>::tgt_adapter == nullptr)
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vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using vm_base<ARCH>::get_reg_ptr;
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = std::tuple<continuation_e>;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, std::ostringstream&);
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inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
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template <typename T> inline ConstantInt *size(T type) {
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return nullptr;
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}
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void setup_module(std::string m) override {
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super::setup_module(m);
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}
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inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
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return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
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}
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compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, std::ostringstream&) override;
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void gen_leave_behavior(std::ostringstream& os) override;
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void gen_raise_trap(uint16_t trap_id, uint16_t cause);
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void gen_leave_trap(unsigned lvl);
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void gen_wait(unsigned type);
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void gen_trap_behavior(std::ostringstream& os) override;
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void gen_trap_check(std::ostringstream& os){
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os<< fmt::format("if(*(uint32_t){})!=0) goto trap_blk;\n", get_reg_ptr(arch::traits<ARCH>::TRAP_STATE));
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}
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inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
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return this->builder.CreateLoad(get_reg_ptr(i), false);
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}
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inline void gen_set_pc(std::ostringstream& os, virt_addr_t pc, unsigned reg_num) {
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os<< fmt::format("*((uint64_t*){}) = {}\n", get_reg_ptr(reg_num), pc.val);
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}
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<InstructionDesriptor, 52> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */
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/* instruction LUI */
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{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
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/* instruction AUIPC */
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{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
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/* instruction JAL */
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{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
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/* instruction JALR */
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{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
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/* instruction BEQ */
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{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
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/* instruction BNE */
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{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
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/* instruction BLT */
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{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
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/* instruction BGE */
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{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
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/* instruction BLTU */
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{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
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/* instruction BGEU */
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{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
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/* instruction LB */
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{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
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/* instruction LH */
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{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
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/* instruction LW */
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{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
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/* instruction LBU */
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{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
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/* instruction LHU */
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{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
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/* instruction SB */
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{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
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/* instruction SH */
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{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
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/* instruction SW */
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{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
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/* instruction ADDI */
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{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
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/* instruction SLTI */
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{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
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/* instruction SLTIU */
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{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
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/* instruction XORI */
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{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
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/* instruction ORI */
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{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
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/* instruction ANDI */
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{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
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/* instruction SLLI */
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{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
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/* instruction SRLI */
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{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
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/* instruction SRAI */
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{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
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/* instruction ADD */
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{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
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/* instruction SUB */
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{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
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/* instruction SLL */
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{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
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/* instruction SLT */
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{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
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/* instruction SLTU */
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{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
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/* instruction XOR */
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{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
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/* instruction SRL */
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{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
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/* instruction SRA */
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{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
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/* instruction OR */
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{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
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/* instruction AND */
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{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
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/* instruction FENCE */
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{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
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/* instruction FENCE_I */
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{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
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/* instruction ECALL */
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{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
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/* instruction EBREAK */
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{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
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/* instruction URET */
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{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
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/* instruction SRET */
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{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
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/* instruction MRET */
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{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
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/* instruction WFI */
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{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
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/* instruction SFENCE.VMA */
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{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
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/* instruction CSRRW */
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{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
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/* instruction CSRRS */
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{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
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/* instruction CSRRC */
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{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
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/* instruction CSRRWI */
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{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
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/* instruction CSRRSI */
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{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
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/* instruction CSRRCI */
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{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
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}};
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/* instruction definitions */
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/* instruction 0: LUI */
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compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 1: AUIPC */
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compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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os<<fmt::format("AUIPC-{:%08x}:\n", pc.val);
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this->gen_sync(os, PRE_SYNC, 1);
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uint8_t rd = ((bit_sub<7,5>(instr)));
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int32_t imm = signextend<int32_t,32>((bit_sub<12,20>(instr) << 12));
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if(this->disass_enabled){
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/* generate console output when executing the command */
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auto mnemonic = fmt::format(
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"{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
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fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
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os<<fmt::format("\tprint_disass((void*){}, {}, {});\n", this->core_ptr, pc.val, mnemonic);
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}
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Value* cur_pc_val = this->gen_const(64, pc.val);
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pc=pc+4;
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if(rd != 0){
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os<<fmt::format("uint64_t res = {} + {};\n", cur_pc_val, imm);
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os<<fmt::format("*((uint64_t*){}) = ret\n", get_reg_ptr(rd + traits<ARCH>::X0));
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}
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this->gen_set_pc(os, pc, traits<ARCH>::NEXT_PC);
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this->gen_sync(os, POST_SYNC, 1);
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this->gen_trap_check(os);
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return std::make_tuple(CONT);
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}
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/* instruction 2: JAL */
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compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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this->gen_sync(os, PRE_SYNC, 0);
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uint8_t rd = ((bit_sub<7,5>(instr)));
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uint8_t rs1 = ((bit_sub<15,5>(instr)));
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int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
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if(this->disass_enabled){
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/* generate console output when executing the command */
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auto mnemonic = fmt::format(
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"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
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fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
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os<<"print_disass(0x"<<std::hex<<this->core_ptr<<", 0x"<<pc.val<<", \""<<mnemonic<<"\");\n";
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}
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auto cur_pc_val = pc.val;
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pc=pc+4;
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}
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/* instruction 3: JALR */
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compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 4: BEQ */
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compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 5: BNE */
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compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 6: BLT */
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compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 7: BGE */
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compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 8: BLTU */
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compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 9: BGEU */
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compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 10: LB */
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compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 11: LH */
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compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 12: LW */
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compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 13: LBU */
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compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 14: LHU */
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compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 15: SB */
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compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 16: SH */
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compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 17: SW */
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compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 18: ADDI */
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compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 19: SLTI */
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compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 20: SLTIU */
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compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 21: XORI */
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compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 22: ORI */
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compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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/* instruction 23: ANDI */
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compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 24: SLLI */
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compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 25: SRLI */
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compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 26: SRAI */
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compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 27: ADD */
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compile_ret_t __add(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 28: SUB */
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compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 29: SLL */
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compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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/* instruction 30: SLT */
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compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
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|
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|
/* instruction 31: SLTU */
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compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 32: XOR */
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|
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 33: SRL */
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|
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
|
|
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/* instruction 34: SRA */
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compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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}
|
|
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|
/* instruction 35: OR */
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|
compile_ret_t __or(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 36: AND */
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|
compile_ret_t __and(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 37: FENCE */
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|
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 38: FENCE_I */
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|
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
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|
}
|
|
|
|
/* instruction 39: ECALL */
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|
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 40: EBREAK */
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|
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 41: URET */
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|
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 42: SRET */
|
|
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 43: MRET */
|
|
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 44: WFI */
|
|
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 45: SFENCE.VMA */
|
|
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 46: CSRRW */
|
|
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 47: CSRRS */
|
|
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 48: CSRRC */
|
|
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 49: CSRRWI */
|
|
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 50: CSRRSI */
|
|
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/* instruction 51: CSRRCI */
|
|
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, std::ostringstream& os){
|
|
}
|
|
|
|
/****************************************************************************
|
|
* end opcode definitions
|
|
****************************************************************************/
|
|
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::ostringstream& os) {
|
|
this->gen_sync(os, iss::PRE_SYNC, instr_descr.size());
|
|
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
|
gen_raise_trap(0, 2); // illegal instruction trap
|
|
this->gen_sync(os, iss::POST_SYNC, instr_descr.size());
|
|
this->gen_trap_check(os);
|
|
return BRANCH;
|
|
}
|
|
};
|
|
|
|
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
|
volatile CODE_WORD x = insn;
|
|
insn = 2 * x;
|
|
}
|
|
|
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
|
|
|
template <typename ARCH>
|
|
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
|
: vm_base<ARCH>(core, core_id, cluster_id) {
|
|
qlut[0] = lut_00.data();
|
|
qlut[1] = lut_01.data();
|
|
qlut[2] = lut_10.data();
|
|
qlut[3] = lut_11.data();
|
|
for (auto instr : instr_descr) {
|
|
auto quantrant = instr.value & 0x3;
|
|
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
|
}
|
|
}
|
|
|
|
template <typename ARCH>
|
|
std::tuple<continuation_e>
|
|
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, std::ostringstream& os) {
|
|
// we fetch at max 4 byte, alignment is 2
|
|
enum {TRAP_ID=1<<16};
|
|
code_word_t insn = 0;
|
|
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
|
phys_addr_t paddr(pc);
|
|
auto *const data = (uint8_t *)&insn;
|
|
paddr = this->core.v2p(pc);
|
|
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
|
auto res = this->core.read(paddr, 2, data);
|
|
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
|
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
|
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
|
}
|
|
} else {
|
|
auto res = this->core.read(paddr, 4, data);
|
|
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
|
}
|
|
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
|
// curr pc on stack
|
|
++inst_cnt;
|
|
auto lut_val = extract_fields(insn);
|
|
auto f = qlut[insn & 0x3][lut_val];
|
|
if (f == nullptr) {
|
|
f = &this_class::illegal_intruction;
|
|
}
|
|
return (this->*f)(pc, insn, os);
|
|
}
|
|
|
|
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(std::ostringstream& os) {
|
|
}
|
|
|
|
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
|
}
|
|
|
|
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
|
}
|
|
|
|
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
|
}
|
|
|
|
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(std::ostringstream& os) {
|
|
}
|
|
|
|
} // namespace mnrv32
|
|
|
|
template <>
|
|
std::unique_ptr<vm_if> create<arch::mnrv32>(arch::mnrv32 *core, unsigned short port, bool dump) {
|
|
auto ret = new mnrv32::vm_impl<arch::mnrv32>(*core, dump);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
return std::unique_ptr<vm_if>(ret);
|
|
}
|
|
}
|
|
} // namespace iss
|