856 lines
32 KiB
C++
856 lines
32 KiB
C++
/*******************************************************************************
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* Copyright (C) 2017 - 2025 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial implementation
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******************************************************************************/
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#ifndef _RISCV_HART_COMMON
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#define _RISCV_HART_COMMON
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#include "iss/arch/traits.h"
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#include "iss/log_categories.h"
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#include "iss/mmio/memory_if.h"
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#include "iss/vm_types.h"
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#include "mstatus.h"
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#include "util/delegate.h"
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#include <array>
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#include <cstdint>
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#include <elfio/elfio.hpp>
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#include <fmt/format.h>
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#include <iss/arch_if.h>
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#include <iss/log_categories.h>
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#include <iss/semihosting/semihosting.h>
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#include <limits>
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#include <sstream>
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#include <string>
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#include <unordered_map>
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#include <util/logging.h>
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#include <util/sparse_array.h>
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#if defined(__GNUC__)
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#define likely(x) ::__builtin_expect(!!(x), 1)
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#define unlikely(x) ::__builtin_expect(!!(x), 0)
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#else
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#define likely(x) x
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#define unlikely(x) x
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#endif
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namespace iss {
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namespace arch {
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enum features_e { FEAT_NONE, FEAT_EXT_N = 1, FEAT_DEBUG = 2 };
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enum riscv_csr {
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/* user-level CSR */
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// User Trap Setup
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ustatus = 0x000,
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uie = 0x004,
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utvec = 0x005,
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utvt = 0x007, // CLIC
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// User Trap Handling
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uscratch = 0x040,
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uepc = 0x041,
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ucause = 0x042,
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utval = 0x043,
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uip = 0x044,
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uxnti = 0x045, // CLIC
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uintstatus = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
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uintthresh = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
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uscratchcsw = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
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uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
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// User Floating-Point CSRs
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fflags = 0x001,
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frm = 0x002,
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fcsr = 0x003,
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// User Counter/Timers
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cycle = 0xC00,
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time = 0xC01,
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instret = 0xC02,
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hpmcounter3 = 0xC03,
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hpmcounter4 = 0xC04,
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/*...*/
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hpmcounter31 = 0xC1F,
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cycleh = 0xC80,
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timeh = 0xC81,
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instreth = 0xC82,
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hpmcounter3h = 0xC83,
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hpmcounter4h = 0xC84,
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/*...*/
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hpmcounter31h = 0xC9F,
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/* supervisor-level CSR */
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// Supervisor Trap Setup
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sstatus = 0x100,
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sedeleg = 0x102,
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sideleg = 0x103,
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sie = 0x104,
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stvec = 0x105,
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scounteren = 0x106,
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// Supervisor Trap Handling
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sscratch = 0x140,
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sepc = 0x141,
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scause = 0x142,
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stval = 0x143,
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sip = 0x144,
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// Supervisor Protection and Translation
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satp = 0x180,
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/* machine-level CSR */
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// Machine Information Registers
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mvendorid = 0xF11,
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marchid = 0xF12,
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mimpid = 0xF13,
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mhartid = 0xF14,
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// Machine Trap Setup
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mstatus = 0x300,
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misa = 0x301,
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medeleg = 0x302,
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mideleg = 0x303,
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mie = 0x304,
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mtvec = 0x305,
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mcounteren = 0x306,
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mtvt = 0x307, // CLIC
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// Machine Trap Handling
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mscratch = 0x340,
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mepc = 0x341,
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mcause = 0x342,
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mtval = 0x343,
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mip = 0x344,
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mxnti = 0x345, // CLIC
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mintstatus = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
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mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
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mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
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mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
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// Physical Memory Protection
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pmpcfg0 = 0x3A0,
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pmpcfg1 = 0x3A1,
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pmpcfg2 = 0x3A2,
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pmpcfg3 = 0x3A3,
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pmpaddr0 = 0x3B0,
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pmpaddr1 = 0x3B1,
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pmpaddr2 = 0x3B2,
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pmpaddr3 = 0x3B3,
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pmpaddr4 = 0x3B4,
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pmpaddr5 = 0x3B5,
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pmpaddr6 = 0x3B6,
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pmpaddr7 = 0x3B7,
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pmpaddr8 = 0x3B8,
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pmpaddr9 = 0x3B9,
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pmpaddr10 = 0x3BA,
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pmpaddr11 = 0x3BB,
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pmpaddr12 = 0x3BC,
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pmpaddr13 = 0x3BD,
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pmpaddr14 = 0x3BE,
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pmpaddr15 = 0x3BF,
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// Machine Counter/Timers
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mcycle = 0xB00,
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minstret = 0xB02,
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mhpmcounter3 = 0xB03,
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mhpmcounter4 = 0xB04,
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/*...*/
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mhpmcounter31 = 0xB1F,
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mcycleh = 0xB80,
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minstreth = 0xB82,
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mhpmcounter3h = 0xB83,
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mhpmcounter4h = 0xB84,
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/*...*/
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mhpmcounter31h = 0xB9F,
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// Machine Counter Setup
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mhpmevent3 = 0x323,
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mhpmevent4 = 0x324,
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/*...*/
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mhpmevent31 = 0x33F,
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// Debug/Trace Registers (shared with Debug Mode)
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tselect = 0x7A0,
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tdata1 = 0x7A1,
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tdata2 = 0x7A2,
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tdata3 = 0x7A3,
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// Debug Mode Registers
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dcsr = 0x7B0,
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dpc = 0x7B1,
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dscratch0 = 0x7B2,
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dscratch1 = 0x7B3
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};
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enum {
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PGSHIFT = 12,
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PTE_PPN_SHIFT = 10,
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// page table entry (PTE) fields
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PTE_V = 0x001, // Valid
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PTE_R = 0x002, // Read
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PTE_W = 0x004, // Write
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PTE_X = 0x008, // Execute
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PTE_U = 0x010, // User
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PTE_G = 0x020, // Global
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PTE_A = 0x040, // Accessed
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PTE_D = 0x080, // Dirty
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PTE_SOFT = 0x300 // Reserved for Software
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};
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template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
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enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4 };
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enum {
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ISA_A = 1,
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ISA_B = 1 << 1,
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ISA_C = 1 << 2,
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ISA_D = 1 << 3,
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ISA_E = 1 << 4,
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ISA_F = 1 << 5,
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ISA_G = 1 << 6,
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ISA_I = 1 << 8,
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ISA_M = 1 << 12,
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ISA_N = 1 << 13,
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ISA_Q = 1 << 16,
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ISA_S = 1 << 18,
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ISA_U = 1 << 20
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};
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struct vm_info {
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int levels;
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int idxbits;
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int ptesize;
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uint64_t ptbase;
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bool is_active() { return levels; }
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};
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struct feature_config {
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uint64_t tcm_base{0x10000000};
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uint64_t tcm_size{0x8000};
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uint64_t io_address{0xf0000000};
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uint64_t io_addr_mask{0xf0000000};
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};
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class trap_load_access_fault : public trap_access {
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public:
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trap_load_access_fault(uint64_t badaddr)
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: trap_access(5 << 16, badaddr) {}
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};
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class illegal_instruction_fault : public trap_access {
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public:
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illegal_instruction_fault(uint64_t badaddr)
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: trap_access(2 << 16, badaddr) {}
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};
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class trap_instruction_page_fault : public trap_access {
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public:
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trap_instruction_page_fault(uint64_t badaddr)
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: trap_access(12 << 16, badaddr) {}
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};
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class trap_load_page_fault : public trap_access {
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public:
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trap_load_page_fault(uint64_t badaddr)
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: trap_access(13 << 16, badaddr) {}
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};
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class trap_store_page_fault : public trap_access {
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public:
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trap_store_page_fault(uint64_t badaddr)
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: trap_access(15 << 16, badaddr) {}
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};
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template <typename WORD_TYPE> struct priv_if {
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using rd_csr_f = std::function<iss::status(unsigned addr, WORD_TYPE&)>;
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using wr_csr_f = std::function<iss::status(unsigned addr, WORD_TYPE)>;
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std::function<iss::status(unsigned, WORD_TYPE&)> read_csr;
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std::function<iss::status(unsigned, WORD_TYPE)> write_csr;
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std::function<iss::status(uint8_t const*)> exec_htif;
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std::unordered_map<unsigned, rd_csr_f>& csr_rd_cb;
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std::unordered_map<unsigned, wr_csr_f>& csr_wr_cb;
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hart_state<WORD_TYPE>& mstatus;
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uint64_t& tohost;
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uint64_t& fromhost;
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unsigned& mcause_max_irq;
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};
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template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_common : public BASE, public mmio::memory_elem {
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const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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const std::array<const char*, 16> trap_str = {{""
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"Instruction address misaligned", // 0
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"Instruction access fault", // 1
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"Illegal instruction", // 2
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"Breakpoint", // 3
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"Load address misaligned", // 4
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"Load access fault", // 5
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"Store/AMO address misaligned", // 6
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"Store/AMO access fault", // 7
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"Environment call from U-mode", // 8
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"Environment call from S-mode", // 9
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"Reserved", // a
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"Environment call from M-mode", // b
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"Instruction page fault", // c
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"Load page fault", // d
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"Reserved", // e
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"Store/AMO page fault"}};
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const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
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"Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
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"Reserved", "Machine timer interrupt", "User external interrupt",
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"Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
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constexpr static unsigned MEM = traits<BASE>::MEM;
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using core = BASE;
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using this_class = riscv_hart_common<BASE, LOGCAT>;
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using phys_addr_t = typename core::phys_addr_t;
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using reg_t = typename core::reg_t;
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using addr_t = typename core::addr_t;
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using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
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using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
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#define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); };
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#define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); };
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riscv_hart_common()
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: state()
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, instr_if(*this) {
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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csr[marchid] = traits<BASE>::MARCHID_VAL;
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csr[mimpid] = 1;
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if(traits<BASE>::FLEN > 0) {
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csr_rd_cb[fcsr] = MK_CSR_RD_CB(read_fcsr);
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csr_wr_cb[fcsr] = MK_CSR_WR_CB(write_fcsr);
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csr_rd_cb[fflags] = MK_CSR_RD_CB(read_fcsr);
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csr_wr_cb[fflags] = MK_CSR_WR_CB(write_fcsr);
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csr_rd_cb[frm] = MK_CSR_RD_CB(read_fcsr);
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csr_wr_cb[frm] = MK_CSR_WR_CB(write_fcsr);
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}
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for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
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csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
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}
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if(traits<BASE>::XLEN == 32)
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for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
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csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
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}
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for(unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
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csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
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}
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for(unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
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}
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if(traits<BASE>::XLEN == 32)
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for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
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}
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// common regs
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const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
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for(auto addr : roaddrs) {
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csr_rd_cb[addr] = MK_CSR_RD_CB(read_plain);
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csr_wr_cb[addr] = MK_CSR_WR_CB(write_null);
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}
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// special handling & overrides
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csr_rd_cb[time] = MK_CSR_RD_CB(read_time);
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if(traits<BASE>::XLEN == 32)
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csr_rd_cb[timeh] = MK_CSR_RD_CB(read_time);
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csr_rd_cb[cycle] = MK_CSR_RD_CB(read_cycle);
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if(traits<BASE>::XLEN == 32)
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csr_rd_cb[cycleh] = MK_CSR_RD_CB(read_cycle);
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csr_rd_cb[instret] = MK_CSR_RD_CB(read_instret);
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if(traits<BASE>::XLEN == 32)
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csr_rd_cb[instreth] = MK_CSR_RD_CB(read_instret);
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csr_rd_cb[mcycle] = MK_CSR_RD_CB(read_cycle);
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csr_wr_cb[mcycle] = MK_CSR_WR_CB(write_cycle);
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if(traits<BASE>::XLEN == 32)
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csr_rd_cb[mcycleh] = MK_CSR_RD_CB(read_cycle);
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if(traits<BASE>::XLEN == 32)
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csr_wr_cb[mcycleh] = MK_CSR_WR_CB(write_cycle);
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csr_rd_cb[minstret] = MK_CSR_RD_CB(read_instret);
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csr_wr_cb[minstret] = MK_CSR_WR_CB(write_instret);
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if(traits<BASE>::XLEN == 32)
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csr_rd_cb[minstreth] = MK_CSR_RD_CB(read_instret);
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if(traits<BASE>::XLEN == 32)
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csr_wr_cb[minstreth] = MK_CSR_WR_CB(write_instret);
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csr_rd_cb[mhartid] = MK_CSR_RD_CB(read_hartid);
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};
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~riscv_hart_common() {
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if(io_buf.str().length()) {
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CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
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}
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}
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std::unordered_map<std::string, uint64_t> symbol_table;
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uint64_t entry_address{0};
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uint64_t tohost = std::numeric_limits<uint64_t>::max();
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uint64_t fromhost = std::numeric_limits<uint64_t>::max();
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std::stringstream io_buf;
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void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
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std::pair<uint64_t, bool> load_file(std::string name, int type) {
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return std::make_pair(entry_address, read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64));
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}
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bool read_elf_file(std::string name, uint8_t expected_elf_class) {
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// Create elfio reader
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ELFIO::elfio reader;
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// Load ELF data
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if(reader.load(name)) {
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// check elf properties
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if(reader.get_class() != expected_elf_class)
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return false;
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if(reader.get_type() != ELFIO::ET_EXEC)
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return false;
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if(reader.get_machine() != ELFIO::EM_RISCV)
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return false;
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entry_address = reader.get_entry();
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for(const auto& pseg : reader.segments) {
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const auto fsize = pseg->get_file_size(); // 0x42c/0x0
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const auto seg_data = pseg->get_data();
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const auto type = pseg->get_type();
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if(type == ELFIO::PT_LOAD && fsize > 0) {
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auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
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pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
|
|
if(res != iss::Ok)
|
|
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
|
|
}
|
|
}
|
|
const auto sym_sec = reader.sections[".symtab"];
|
|
if(ELFIO::SHT_SYMTAB == sym_sec->get_type() || ELFIO::SHT_DYNSYM == sym_sec->get_type()) {
|
|
ELFIO::symbol_section_accessor symbols(reader, sym_sec);
|
|
auto sym_no = symbols.get_symbols_num();
|
|
std::string name;
|
|
ELFIO::Elf64_Addr value = 0;
|
|
ELFIO::Elf_Xword size = 0;
|
|
unsigned char bind = 0;
|
|
unsigned char type = 0;
|
|
ELFIO::Elf_Half section = 0;
|
|
unsigned char other = 0;
|
|
for(auto i = 0U; i < sym_no; ++i) {
|
|
symbols.get_symbol(i, name, value, size, bind, type, section, other);
|
|
if(name != "") {
|
|
this->symbol_table[name] = value;
|
|
#ifndef NDEBUG
|
|
CPPLOG(DEBUG) << "Found Symbol " << name;
|
|
#endif
|
|
}
|
|
}
|
|
try {
|
|
tohost = symbol_table.at("tohost");
|
|
} catch(std::out_of_range& e) {
|
|
}
|
|
try {
|
|
fromhost = symbol_table.at("fromhost");
|
|
} catch(std::out_of_range& e) {
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
return false;
|
|
};
|
|
|
|
iss::status execute_sys_write(arch_if* aif, const std::array<uint64_t, 8>& loaded_payload, unsigned mem_type) {
|
|
uint64_t fd = loaded_payload[1];
|
|
uint64_t buf_ptr = loaded_payload[2];
|
|
uint64_t len = loaded_payload[3];
|
|
std::vector<char> buf(len);
|
|
if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast<uint8_t*>(buf.data()))) {
|
|
CPPLOG(ERR) << "SYS_WRITE buffer read went wrong";
|
|
return iss::Err;
|
|
}
|
|
// we disregard the fd and just log to stdout
|
|
for(size_t i = 0; i < len; i++) {
|
|
if(buf[i] == '\n' || buf[i] == '\0') {
|
|
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
|
|
io_buf.str("");
|
|
} else
|
|
io_buf << buf[i];
|
|
}
|
|
|
|
// Not sure what the correct return value should be
|
|
uint8_t ret_val = 1;
|
|
if(fromhost != std::numeric_limits<uint64_t>::max())
|
|
if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) {
|
|
CPPLOG(ERR) << "Fromhost write went wrong";
|
|
return iss::Err;
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
constexpr bool has_compressed() { return traits<BASE>::MISA_VAL & 0b0100; }
|
|
|
|
constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; }
|
|
|
|
void disass_output(uint64_t pc, const std::string instr) override {
|
|
// NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV],
|
|
// (reg_t)state.mstatus,
|
|
// this->reg.cycle + cycle_offset);
|
|
NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};c:{}]", pc, instr, lvl[this->reg.PRIV],
|
|
this->reg.cycle + cycle_offset);
|
|
};
|
|
|
|
void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; }
|
|
void register_csr(unsigned addr, wr_csr_f f) { csr_wr_cb[addr] = f; }
|
|
void register_csr(unsigned addr, rd_csr_f rdf, wr_csr_f wrf) {
|
|
csr_rd_cb[addr] = rdf;
|
|
csr_wr_cb[addr] = wrf;
|
|
}
|
|
void unregister_csr_rd(unsigned addr) { csr_rd_cb.erase(addr); }
|
|
void unregister_csr_wr(unsigned addr) { csr_wr_cb.erase(addr); }
|
|
|
|
bool debug_mode_active() { return this->reg.PRIV & 0x4; }
|
|
|
|
const reg_t& get_mhartid() const { return mhartid_reg; }
|
|
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
|
|
|
|
iss::status read_csr(unsigned addr, reg_t& val) {
|
|
if(addr >= csr.size())
|
|
return iss::Err;
|
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
|
if(this->reg.PRIV < req_priv_lvl) // not having required privileges
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
auto it = csr_rd_cb.find(addr);
|
|
if(it == csr_rd_cb.end() || !it->second) // non existent register
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
return it->second(addr, val);
|
|
}
|
|
|
|
iss::status write_csr(unsigned addr, reg_t val) {
|
|
if(addr >= csr.size())
|
|
return iss::Err;
|
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
|
if(this->reg.PRIV < req_priv_lvl) // not having required privileges
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
if((addr & 0xc00) == 0xc00) // writing to read-only region
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
auto it = csr_wr_cb.find(addr);
|
|
if(it == csr_wr_cb.end() || !it->second) // non existent register
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
return it->second(addr, val);
|
|
}
|
|
|
|
iss::status read_null(unsigned addr, reg_t& val) {
|
|
val = 0;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_null(unsigned addr, reg_t val) { return iss::status::Ok; }
|
|
|
|
iss::status read_plain(unsigned addr, reg_t& val) {
|
|
val = csr[addr];
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_plain(unsigned addr, reg_t val) {
|
|
csr[addr] = val;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_cycle(unsigned addr, reg_t& val) {
|
|
auto cycle_val = this->reg.cycle + cycle_offset;
|
|
if(addr == mcycle) {
|
|
val = static_cast<reg_t>(cycle_val);
|
|
} else if(addr == mcycleh) {
|
|
val = static_cast<reg_t>(cycle_val >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_cycle(unsigned addr, reg_t val) {
|
|
if(sizeof(typename traits<BASE>::reg_t) != 4) {
|
|
mcycle_csr = static_cast<uint64_t>(val);
|
|
} else {
|
|
if(addr == mcycle) {
|
|
mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
|
|
} else {
|
|
mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
|
|
}
|
|
}
|
|
cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_instret(unsigned addr, reg_t& val) {
|
|
if((addr & 0xff) == (minstret & 0xff)) {
|
|
val = static_cast<reg_t>(this->reg.instret);
|
|
} else if((addr & 0xff) == (minstreth & 0xff)) {
|
|
val = static_cast<reg_t>(this->reg.instret >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_instret(unsigned addr, reg_t val) {
|
|
if(sizeof(typename traits<BASE>::reg_t) != 4) {
|
|
this->reg.instret = static_cast<uint64_t>(val);
|
|
} else {
|
|
if((addr & 0xff) == (minstret & 0xff)) {
|
|
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
|
|
} else {
|
|
this->reg.instret = (static_cast<uint64_t>(val) << 32) + (this->reg.instret & 0xffffffff);
|
|
}
|
|
}
|
|
this->reg.instret--;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_time(unsigned addr, reg_t& val) {
|
|
uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
|
|
if(addr == time) {
|
|
val = static_cast<reg_t>(time_val);
|
|
} else if(addr == timeh) {
|
|
if(sizeof(typename traits<BASE>::reg_t) != 4)
|
|
return iss::Err;
|
|
val = static_cast<reg_t>(time_val >> 32);
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_tvec(unsigned addr, reg_t& val) {
|
|
val = csr[addr] & ~2;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_hartid(unsigned addr, reg_t& val) {
|
|
val = mhartid_reg;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_epc(unsigned addr, reg_t val) {
|
|
csr[addr] = val & get_pc_mask();
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_dcsr(unsigned addr, reg_t val) {
|
|
if(!debug_mode_active())
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
// +-------------- ebreakm
|
|
// | +---------- stepi
|
|
// | | +++----- cause
|
|
// | | ||| +- step
|
|
csr[addr] = val & 0b1000100111000100U;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_debug(unsigned addr, reg_t& val) {
|
|
if(!debug_mode_active())
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
val = csr[addr];
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_dscratch(unsigned addr, reg_t val) {
|
|
if(!debug_mode_active())
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
csr[addr] = val;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_dpc(unsigned addr, reg_t& val) {
|
|
if(!debug_mode_active())
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
val = this->reg.DPC;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_dpc(unsigned addr, reg_t val) {
|
|
if(!debug_mode_active())
|
|
throw illegal_instruction_fault(this->fault_data);
|
|
this->reg.DPC = val;
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status read_fcsr(unsigned addr, reg_t& val) {
|
|
switch(addr) {
|
|
case 1: // fflags, 4:0
|
|
val = bit_sub<0, 5>(this->get_fcsr());
|
|
break;
|
|
case 2: // frm, 7:5
|
|
val = bit_sub<5, 3>(this->get_fcsr());
|
|
break;
|
|
case 3: // fcsr
|
|
val = this->get_fcsr();
|
|
break;
|
|
default:
|
|
return iss::Err;
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
iss::status write_fcsr(unsigned addr, reg_t val) {
|
|
switch(addr) {
|
|
case 1: // fflags, 4:0
|
|
this->set_fcsr((this->get_fcsr() & 0xffffffe0) | (val & 0x1f));
|
|
break;
|
|
case 2: // frm, 7:5
|
|
this->set_fcsr((this->get_fcsr() & 0xffffff1f) | ((val & 0x7) << 5));
|
|
break;
|
|
case 3: // fcsr
|
|
this->set_fcsr(val & 0xff);
|
|
break;
|
|
default:
|
|
return iss::Err;
|
|
}
|
|
return iss::Ok;
|
|
}
|
|
|
|
priv_if<reg_t> get_priv_if() {
|
|
return priv_if<reg_t>{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
|
|
.write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
|
|
.exec_htif = [this](uint8_t const* data) -> iss::status { return execute_htif(data); },
|
|
.csr_rd_cb{this->csr_rd_cb},
|
|
.csr_wr_cb{csr_wr_cb},
|
|
.mstatus{this->state},
|
|
.tohost{this->tohost},
|
|
.fromhost{this->fromhost},
|
|
.mcause_max_irq{mcause_max_irq}};
|
|
}
|
|
|
|
iss::status execute_htif(uint8_t const* data) {
|
|
reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
|
|
// Extract Device (bits 63:56)
|
|
uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
|
|
// Extract Command (bits 55:48)
|
|
uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
|
|
// Extract payload (bits 47:0)
|
|
uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
|
|
if(payload_addr & 1) {
|
|
CPPLOG(FATAL) << "this->tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
|
|
<< "), stopping simulation";
|
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
|
this->interrupt_sim = payload_addr;
|
|
return iss::Ok;
|
|
} else if(device == 0 && command == 0) {
|
|
std::array<uint64_t, 8> loaded_payload;
|
|
if(memory.rd_mem(access_type::DEBUG_READ, payload_addr, 8 * sizeof(uint64_t),
|
|
reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
|
|
CPPLOG(ERR) << "Syscall read went wrong";
|
|
uint64_t syscall_num = loaded_payload.at(0);
|
|
if(syscall_num == 64) { // SYS_WRITE
|
|
return this->execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
|
|
} else {
|
|
CPPLOG(ERR) << "this->tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
|
|
<< ") not implemented";
|
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
|
this->interrupt_sim = payload_addr;
|
|
return iss::Ok;
|
|
}
|
|
} else {
|
|
CPPLOG(ERR) << "this->tohost functionality not implemented for device " << device << " and command " << command;
|
|
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
|
|
this->interrupt_sim = payload_addr;
|
|
return iss::Ok;
|
|
}
|
|
}
|
|
|
|
mmio::memory_hierarchy memories;
|
|
|
|
virtual mmio::memory_if get_mem_if() override {
|
|
assert(false || "This function should nevver be called");
|
|
return mmio::memory_if{};
|
|
}
|
|
|
|
virtual void set_next(mmio::memory_if mem_if) { memory = mem_if; };
|
|
|
|
void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
|
|
|
|
protected:
|
|
hart_state<reg_t> state;
|
|
|
|
static constexpr reg_t get_mstatus_mask_t(unsigned priv_lvl = PRIV_M) {
|
|
if(sizeof(reg_t) == 4) {
|
|
return priv_lvl == PRIV_U ? 0x80000011UL : // 0b1...0 0001 0001
|
|
priv_lvl == PRIV_S ? 0x800de133UL // 0b0...0 0001 1000 1001 1001;
|
|
: 0x807ff9ddUL;
|
|
} else {
|
|
return priv_lvl == PRIV_U ? 0x011ULL : // 0b1...0 0001 0001
|
|
priv_lvl == PRIV_S ? 0x000de133ULL
|
|
: 0x007ff9ddULL;
|
|
}
|
|
}
|
|
|
|
mmio::memory_if memory;
|
|
struct riscv_instrumentation_if : public iss::instrumentation_if {
|
|
|
|
riscv_instrumentation_if(riscv_hart_common<BASE, LOGCAT>& arch)
|
|
: arch(arch) {}
|
|
/**
|
|
* get the name of this architecture
|
|
*
|
|
* @return the name of this architecture
|
|
*/
|
|
const std::string core_type_name() const override { return traits<BASE>::core_type; }
|
|
|
|
uint64_t get_pc() override { return arch.reg.PC; }
|
|
|
|
uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
|
|
|
|
uint64_t get_instr_word() override { return arch.reg.instruction; }
|
|
|
|
uint64_t get_instr_count() override { return arch.reg.icount; }
|
|
|
|
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
|
|
|
|
uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
|
|
|
|
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
|
|
|
|
bool is_branch_taken() override { return arch.reg.last_branch; }
|
|
|
|
unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
|
|
|
|
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
|
|
|
|
std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
|
|
|
|
riscv_hart_common<BASE, LOGCAT>& arch;
|
|
};
|
|
|
|
friend struct riscv_instrumentation_if;
|
|
riscv_instrumentation_if instr_if;
|
|
|
|
instrumentation_if* get_instrumentation_if() override { return &instr_if; };
|
|
|
|
using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
|
|
using csr_page_type = typename csr_type::page_type;
|
|
csr_type csr;
|
|
|
|
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
|
|
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
|
|
|
|
reg_t mhartid_reg{0x0};
|
|
uint64_t mcycle_csr{0};
|
|
uint64_t minstret_csr{0};
|
|
reg_t fault_data;
|
|
|
|
int64_t cycle_offset{0};
|
|
int64_t instret_offset{0};
|
|
semihosting_cb_t<reg_t> semihosting_cb;
|
|
std::array<vm_info, 2> vm;
|
|
unsigned mcause_max_irq{16U};
|
|
};
|
|
|
|
} // namespace arch
|
|
} // namespace iss
|
|
|
|
#endif
|