1776 lines
101 KiB
C++
1776 lines
101 KiB
C++
/*******************************************************************************
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* Copyright (C) 2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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// clang-format off
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#include <iss/arch/tgc5a.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/interp/vm_base.h>
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#include <vm/fp_functions.h>
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#include <util/logging.h>
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#include <boost/coroutine2/all.hpp>
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#include <functional>
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#include <exception>
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#include <vector>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace interp {
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namespace tgc5a {
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using namespace iss::arch;
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using namespace iss::debugger;
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using namespace std::placeholders;
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struct memory_access_exception : public std::exception{
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memory_access_exception(){}
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};
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
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using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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using opcode_e = typename traits::opcode_e;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (super::tgt_adapter == nullptr)
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super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return super::tgt_adapter;
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}
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protected:
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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// some compile time constants
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->core.reg.trap_state = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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inline void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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}
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inline void wait(unsigned type){
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this->core.wait_until(type);
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}
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using yield_t = boost::coroutines2::coroutine<void>::push_type;
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using coro_t = boost::coroutines2::coroutine<void>::pull_type;
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std::vector<coro_t> spawn_blocks;
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template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
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inline S sext(U from) {
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auto mask = (1ULL<<W) - 1;
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auto sign_mask = 1ULL<<(W-1);
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return (from & mask) | ((from & sign_mask) ? ~mask : 0);
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}
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inline void process_spawn_blocks() {
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if(spawn_blocks.size()==0) return;
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for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
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if(*it){
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(*it)();
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++it;
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} else
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spawn_blocks.erase(it);
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct instruction_descriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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typename arch::traits<ARCH>::opcode_e op;
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};
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struct decoding_tree_node{
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std::vector<instruction_descriptor> instrs;
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std::vector<decoding_tree_node*> children;
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uint32_t submask = std::numeric_limits<uint32_t>::max();
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uint32_t value;
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decoding_tree_node(uint32_t value) : value(value){}
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};
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decoding_tree_node* root {nullptr};
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const std::array<instruction_descriptor, 49> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */
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{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::LUI},
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{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::AUIPC},
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{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::JAL},
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{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::JALR},
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{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BEQ},
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{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BNE},
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{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLT},
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{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGE},
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{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLTU},
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{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGEU},
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{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LB},
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{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LH},
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{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LW},
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{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LBU},
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{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LHU},
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{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SB},
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{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SH},
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{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SW},
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{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ADDI},
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{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTI},
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{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTIU},
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{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::XORI},
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{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ORI},
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{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ANDI},
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{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLLI},
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{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRLI},
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{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRAI},
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{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::ADD},
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{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SUB},
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{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLL},
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{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLT},
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{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTU},
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{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::XOR},
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{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRL},
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{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRA},
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{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::OR},
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{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::AND},
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{32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE},
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{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::ECALL},
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{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::EBREAK},
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{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::MRET},
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{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::WFI},
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{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRW},
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{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRS},
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{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRC},
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{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRWI},
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{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRSI},
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{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRCI},
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{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE_I},
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}};
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iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
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if(this->core.has_mmu()) {
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auto phys_pc = this->core.virt2phys(pc);
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// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
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// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
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// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
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// return iss::Err;
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// } else {
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if (this->core.read(phys_pc, 4, data) != iss::Ok)
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return iss::Err;
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// }
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} else {
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if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
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return iss::Err;
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}
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return iss::Ok;
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}
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void populate_decoding_tree(decoding_tree_node* root){
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//create submask
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for(auto instr: root->instrs){
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root->submask &= instr.mask;
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}
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//put each instr according to submask&encoding into children
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for(auto instr: root->instrs){
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bool foundMatch = false;
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for(auto child: root->children){
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//use value as identifying trait
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if(child->value == (instr.value&root->submask)){
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child->instrs.push_back(instr);
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foundMatch = true;
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}
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}
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if(!foundMatch){
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decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
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child->instrs.push_back(instr);
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root->children.push_back(child);
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}
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}
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root->instrs.clear();
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//call populate_decoding_tree for all children
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if(root->children.size() >1)
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for(auto child: root->children){
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populate_decoding_tree(child);
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}
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else{
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//sort instrs by value of the mask, this works bc we want to have the least restrictive one last
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std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
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return instr1.mask > instr2.mask;
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});
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}
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}
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typename arch::traits<ARCH>::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){
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if(!node->children.size()){
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if(node->instrs.size() == 1) return node->instrs[0].op;
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for(auto instr : node->instrs){
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if((instr.mask&word) == instr.value) return instr.op;
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}
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}
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else{
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for(auto child : node->children){
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if (child->value == (node->submask&word)){
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return decode_instr(child, word);
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}
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}
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}
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return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
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volatile CODE_WORD x = insn;
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insn = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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// according to
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// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
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#ifdef __GCC__
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constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
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#elif __cplusplus < 201402L
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constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
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constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
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#else
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constexpr size_t bit_count(uint32_t u) {
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size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
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return ((uCount + (uCount >> 3)) & 030707070707) % 63;
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}
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#endif
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
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for(auto instr:instr_descr){
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root->instrs.push_back(instr);
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}
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populate_decoding_tree(root);
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}
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inline bool is_count_limit_enabled(finish_cond_e cond){
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return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
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}
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inline bool is_jump_to_self_enabled(finish_cond_e cond){
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return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF;
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}
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template <typename ARCH>
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typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
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auto pc=start;
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auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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auto& trap_state = this->core.reg.trap_state;
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auto& icount = this->core.reg.icount;
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auto& cycle = this->core.reg.cycle;
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auto& instret = this->core.reg.instret;
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auto& instr = this->core.reg.instruction;
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// we fetch at max 4 byte, alignment is 2
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auto *const data = reinterpret_cast<uint8_t*>(&instr);
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while(!this->core.should_stop() &&
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!(is_count_limit_enabled(cond) && icount >= icount_limit)){
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if(fetch_ins(pc, data)!=iss::Ok){
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this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
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pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
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} else {
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if (is_jump_to_self_enabled(cond) &&
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(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto inst_id = decode_instr(root, instr);
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// pre execution stuff
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this->core.reg.last_branch = 0;
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if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
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try{
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switch(inst_id){
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case arch::traits<ARCH>::opcode_e::LUI: {
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uint8_t rd = ((bit_sub<7,5>(instr)));
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uint32_t imm = ((bit_sub<12,20>(instr) << 12));
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if(this->disass_enabled){
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/* generate console output when executing the command */
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auto mnemonic = fmt::format(
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"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
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fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
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this->core.disass_output(pc.val, mnemonic);
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}
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// used registers
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auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
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*NEXT_PC = *PC + 4;
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// execute instruction
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{
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if(rd >= traits::RFS) {
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raise(0, 2);
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}
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else {
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if(rd != 0) {
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*(X+rd) = (uint32_t)((int32_t)imm);
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}
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}
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}
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break;
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}// @suppress("No break at end of case")
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case arch::traits<ARCH>::opcode_e::AUIPC: {
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uint8_t rd = ((bit_sub<7,5>(instr)));
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uint32_t imm = ((bit_sub<12,20>(instr) << 12));
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if(this->disass_enabled){
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/* generate console output when executing the command */
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auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*PC + (int32_t)imm);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::JAL: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*PC + 4);
|
|
}
|
|
*NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::JALR: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t addr_mask = (uint32_t)- 2;
|
|
uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask);
|
|
if(new_pc % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*PC + 4);
|
|
}
|
|
*NEXT_PC = new_pc;
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BEQ: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(*(X+rs1) == *(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BNE: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(*(X+rs1) != *(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BLT: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BGE: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BLTU: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(*(X+rs1) < *(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::BGEU: {
|
|
uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(*(X+rs1) >= *(X+rs2)) {
|
|
if(imm % traits::INSTR_ALIGNMENT) {
|
|
raise(0, 0);
|
|
}
|
|
else {
|
|
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
|
|
this->core.reg.last_branch = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::LB: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
int8_t res_23 = super::template read_mem<int8_t>(traits::MEM, load_address);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
int8_t res = (int8_t)res_23;
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::LH: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
int16_t res_24 = super::template read_mem<int16_t>(traits::MEM, load_address);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
int16_t res = (int16_t)res_24;
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::LW: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
int32_t res_25 = super::template read_mem<int32_t>(traits::MEM, load_address);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
int32_t res = (int32_t)res_25;
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::LBU: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
uint8_t res_26 = super::template read_mem<uint8_t>(traits::MEM, load_address);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint8_t res = res_26;
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::LHU: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
uint16_t res_27 = super::template read_mem<uint16_t>(traits::MEM, load_address);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint16_t res = res_27;
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)res;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SB: {
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SH: {
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SW: {
|
|
uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
|
|
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::ADDI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLTI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLTIU: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::XORI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::ORI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::ANDI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLLI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) << shamt;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SRLI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) >> shamt;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SRAI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t shamt = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::ADD: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SUB: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLL: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLT: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SLTU: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::XOR: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) ^ *(X+rs2);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SRL: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::SRA: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)));
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::OR: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) | *(X+rs2);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::AND: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t rs2 = ((bit_sub<20,5>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
if(rd != 0) {
|
|
*(X+rd) = *(X+rs1) & *(X+rs2);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::FENCE: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint8_t succ = ((bit_sub<20,4>(instr)));
|
|
uint8_t pred = ((bit_sub<24,4>(instr)));
|
|
uint8_t fm = ((bit_sub<28,4>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
|
|
fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::ECALL: {
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "ecall");
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
raise(0, 11);
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::EBREAK: {
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "ebreak");
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
raise(0, 3);
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::MRET: {
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "mret");
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
leave(3);
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::WFI: {
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
this->core.disass_output(pc.val, "wfi");
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
wait(1);
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRW: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t xrs1 = *(X+rs1);
|
|
if(rd != 0) {
|
|
uint32_t res_28 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_28;
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
*(X+rd) = xrd;
|
|
}
|
|
else {
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrs1);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRS: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t res_29 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_29;
|
|
uint32_t xrs1 = *(X+rs1);
|
|
if(rs1 != 0) {
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
if(rd != 0) {
|
|
*(X+rd) = xrd;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRC: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS || rs1 >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t res_30 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_30;
|
|
uint32_t xrs1 = *(X+rs1);
|
|
if(rs1 != 0) {
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
if(rd != 0) {
|
|
*(X+rd) = xrd;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRWI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t res_31 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_31;
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
if(rd != 0) {
|
|
*(X+rd) = xrd;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRSI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_32;
|
|
if(zimm != 0) {
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
if(rd != 0) {
|
|
*(X+rd) = xrd;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::CSRRCI: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t zimm = ((bit_sub<15,5>(instr)));
|
|
uint16_t csr = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
|
|
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers
|
|
auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
if(rd >= traits::RFS) {
|
|
raise(0, 2);
|
|
}
|
|
else {
|
|
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
uint32_t xrd = res_33;
|
|
if(zimm != 0) {
|
|
super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
if(rd != 0) {
|
|
*(X+rd) = xrd;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
case arch::traits<ARCH>::opcode_e::FENCE_I: {
|
|
uint8_t rd = ((bit_sub<7,5>(instr)));
|
|
uint8_t rs1 = ((bit_sub<15,5>(instr)));
|
|
uint16_t imm = ((bit_sub<20,12>(instr)));
|
|
if(this->disass_enabled){
|
|
/* generate console output when executing the command */
|
|
auto mnemonic = fmt::format(
|
|
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
|
|
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
|
|
this->core.disass_output(pc.val, mnemonic);
|
|
}
|
|
// used registers// calculate next pc value
|
|
*NEXT_PC = *PC + 4;
|
|
// execute instruction
|
|
{
|
|
super::template write_mem<uint32_t>(traits::FENCE, traits::fencei, imm);
|
|
if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
|
|
}
|
|
break;
|
|
}// @suppress("No break at end of case")
|
|
default: {
|
|
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
|
|
raise(0, 2);
|
|
}
|
|
}
|
|
}catch(memory_access_exception& e){}
|
|
// post execution stuff
|
|
process_spawn_blocks();
|
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
|
|
// if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
|
|
// this->core.reg.trap_state = this->core.reg.pending_trap;
|
|
// trap check
|
|
if(trap_state!=0){
|
|
super::core.enter_trap(trap_state, pc.val, instr);
|
|
} else {
|
|
icount++;
|
|
instret++;
|
|
}
|
|
cycle++;
|
|
pc.val=*NEXT_PC;
|
|
this->core.reg.PC = this->core.reg.NEXT_PC;
|
|
this->core.reg.trap_state = this->core.reg.pending_trap;
|
|
}
|
|
}
|
|
return pc;
|
|
}
|
|
|
|
} // namespace tgc5a
|
|
|
|
template <>
|
|
std::unique_ptr<vm_if> create<arch::tgc5a>(arch::tgc5a *core, unsigned short port, bool dump) {
|
|
auto ret = new tgc5a::vm_impl<arch::tgc5a>(*core, dump);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
return std::unique_ptr<vm_if>(ret);
|
|
}
|
|
} // namespace interp
|
|
} // namespace iss
|
|
|
|
#include <iss/arch/riscv_hart_m_p.h>
|
|
#include <iss/arch/riscv_hart_mu_p.h>
|
|
#include <iss/factory.h>
|
|
namespace iss {
|
|
namespace {
|
|
volatile std::array<bool, 2> dummy = {
|
|
core_factory::instance().register_creator("tgc5a|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
|
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5a>();
|
|
auto vm = new interp::tgc5a::vm_impl<arch::tgc5a>(*cpu, false);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
|
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
|
}),
|
|
core_factory::instance().register_creator("tgc5a|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
|
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5a>();
|
|
auto vm = new interp::tgc5a::vm_impl<arch::tgc5a>(*cpu, false);
|
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
|
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
|
})
|
|
};
|
|
}
|
|
}
|
|
// clang-format on
|