141 lines
4.4 KiB
C++
141 lines
4.4 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "sysc/SiFive/gpio.h"
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#include "sysc/sc_comm_singleton.h"
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#include "scc/report.h"
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#include "scc/utilities.h"
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#include "sysc/SiFive/gen/gpio_regs.h"
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namespace sysc {
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gpio::gpio(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMED(pins_io)
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, NAMEDD(gpio_regs, regs)
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, NAMED(write_to_ws, false){
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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SC_METHOD(pins_cb);
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sensitive << pins_io;
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regs->port.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data) -> bool {
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if (!this->regs->in_reset()) {
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reg.put(data);
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// read r_ports and update pins_io
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update_pins();
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}
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return true;
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});
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regs->value.set_read_cb([this](const scc::sc_register<uint32_t> ®, uint32_t& data) -> bool {
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if (!this->regs->in_reset()) {
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// read pins_io and update r_value
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update_value_reg();
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data=reg.get();
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}
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return true;
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});
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}
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gpio::~gpio() {}
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void gpio::before_end_of_elaboration() {
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if(write_to_ws.get_value()) {
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LOG(TRACE)<<"Adding WS handler for "<<(std::string{"/ws/"}+name());
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handler=std::make_shared<WsHandler>();
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sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"}+name()).c_str(), handler);
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}
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}
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void gpio::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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void gpio::clock_cb() {
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this->clk = clk_i.read();
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}
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void gpio::pins_cb(){
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auto inval=pins_io.read();
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std::string msg(inval.to_string());
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sc_core::sc_time now = sc_core::sc_time_stamp();
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if(handler) sc_comm_singleton::inst().execute([this, msg, now](){
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std::stringstream os;
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os << "{\"time\":\"" << now << "\",\"data\":\""<<msg<<"\"}";
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this->handler->send(os.str());
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});
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}
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void gpio::update_value_reg() {
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// read pins_io and update r_value reg
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auto inval = pins_io.read();
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uint32_t res = 0;
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for (size_t i = 0, msk = 1; i < 32; ++i, msk = msk << 1) {
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bool bit_set = false;
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if ((regs->r_input_en & msk) != 0) {
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if (inval.get_bit(1) == sc_dt::Log_1)
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bit_set = true;
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else if (inval.get_bit(1) == sc_dt::Log_Z
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&& (regs->r_pue & msk) != 0)
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bit_set = true;
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}
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if (bit_set) res |= msk;
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}
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regs->r_value = res;
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}
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void gpio::update_pins() {
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sc_core::sc_inout_rv<32>::data_type out_val;
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for(size_t i=0, msk = 1; i<32; ++i, msk=msk<<1)
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out_val.set_bit(i, regs->r_output_en&msk?regs->r_port&msk?sc_dt::Log_1:sc_dt::Log_0:sc_dt::Log_Z);
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pins_io.write(out_val);
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}
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} /* namespace sysc */
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