118 lines
4.6 KiB
Plaintext
118 lines
4.6 KiB
Plaintext
/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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import com.minres.coredsl.coreDsl.RegisterAlias
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def getOriginalName(reg){
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if( reg.original instanceof RegisterFile) {
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if( reg.index != null ) {
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return reg.original.name+generator.generateHostCode(reg.index)
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} else {
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return reg.original.name
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}
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} else if(reg.original instanceof Register){
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return reg.original.name
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}
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}
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def getRegisterNames(){
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def regNames = []
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{
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regNames+=reg.name.toLowerCase()+it
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}
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} else if(reg instanceof Register){
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regNames+=reg.name.toLowerCase()
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}
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}
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return regNames
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}
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def getRegisterAliasNames(){
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def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
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return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
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if( reg instanceof RegisterFile) {
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return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
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} else if(reg instanceof Register){
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regMap[reg.name]?:reg.name.toLowerCase()
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}
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}.flatten()
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}
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%>
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
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constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
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constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
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constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
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${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
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reg.icount = 0;
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}
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${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
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void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
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for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.trap_state=0;
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reg.machine_state=0x0;
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reg.icount=0;
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}
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uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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