486 lines
17 KiB
C++
486 lines
17 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "scc/report.h"
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#include "iss/arch/riscv_hart_msu_vp.h"
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#include "iss/arch/rv32imac.h"
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#include "iss/iss.h"
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#include "iss/vm_types.h"
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#include "iss/debugger/server.h"
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#include "iss/debugger/gdb_session.h"
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#include "iss/debugger/target_adapter_if.h"
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#include "iss/debugger/encoderdecoder.h"
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#include "sysc/core_complex.h"
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#ifdef WITH_SCV
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#include <scv.h>
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#include <array>
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#endif
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namespace sysc {
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namespace SiFive {
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using namespace std;
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using namespace iss;
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namespace {
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iss::debugger::encoder_decoder encdec;
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}
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namespace {
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std::array<const char, 4> lvl = { { 'U', 'S', 'H', 'M' } };
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std::array<const char*, 16> trap_str = { {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"Reserved",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"Reserved",
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"Store/AMO page fault"
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} };
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std::array<const char*, 12> irq_str = { {
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"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
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"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
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}
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class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
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public:
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using core_type = arch::rv32imac;
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using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
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using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
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core_wrapper(core_complex *owner)
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: owner(owner)
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{}
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uint32_t get_mode(){ return this->reg.machine_state; }
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inline
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void set_interrupt_execution(bool v){ this->interrupt_sim=v;}
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inline
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bool get_interrupt_execution(){ return this->interrupt_sim;}
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base_type::hart_state<base_type::reg_t>& get_state() { return this->state; }
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void notify_phase(exec_phase p) override {
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if(p == ISTART) owner->sync(this->reg.icount+cycle_offset);
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}
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sync_type needed_sync() const override { return PRE_SYNC; }
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void disass_output(uint64_t pc, const std::string instr) override {
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if (logging::INFO <= logging::Log<logging::Output2FILE<logging::disass>>::reporting_level() && logging::Output2FILE<logging::disass>::stream()){
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std::stringstream s;
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s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
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scc::Log<logging::Output2FILE<logging::disass>>().get(logging::INFO, "disass")
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<< "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<std::setw(40)<<std::setfill(' ')<<std::left<<instr<<s.str();
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}
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owner->disass_output(pc,instr);
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};
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status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
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if (addr.access && access_type::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
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else {
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return owner->read_mem(addr.val, length, data,addr.access && access_type::FETCH) ? Ok : Err;
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}
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}
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status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
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if (addr.access && access_type::DEBUG)
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return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
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else{
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auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
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// clear MTIP on mtimecmp write
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if(addr.val==0x2004000){
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reg_t val;
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this->read_csr(arch::mip, val);
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this->write_csr(arch::mip, val & ~(1ULL<<7));
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}
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return res;
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}
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}
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void wait_until(uint64_t flags) {
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do{
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wait(wfi_evt);
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this->check_interrupt();
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} while(this->reg.pending_trap==0);
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base_type::wait_until(flags);
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}
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void local_irq(short id){
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switch(id){
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case 16: // SW
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this->csr[arch::mip] |= 1<<3;
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break;
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case 17: // timer
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this->csr[arch::mip] |= 1<<7;
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break;
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case 18: //external
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this->csr[arch::mip] |= 1<<11;
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break;
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default:
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/* do nothing*/
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break;
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}
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wfi_evt.notify();
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}
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private:
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core_complex *const owner;
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sc_event wfi_evt;
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};
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int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter){
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if(argc>1) {
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if(strcasecmp(argv[1], "print_time")==0){
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std::string t = sc_core::sc_time_stamp().to_string();
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of(t.c_str());
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std::array<char, 64> buf;
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encdec.enc_string(t.c_str(), buf.data(), 63);
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df(buf.data());
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return Ok;
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} else if(strcasecmp(argv[1], "break")==0){
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sc_core::sc_time t;
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if(argc==4){
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t= scc::parse_from_string(argv[2], argv[3]);
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} else if(argc==3){
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t= scc::parse_from_string(argv[2]);
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} else
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return Err;
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// no check needed as it is only called if debug server is active
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tgt_adapter->add_break_condition([t]()->unsigned{
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LOG(TRACE)<<"Checking condition at "<<sc_core::sc_time_stamp();
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return sc_core::sc_time_stamp()>=t?std::numeric_limits<unsigned>::max():0;
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});
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return Ok;
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}
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return Err;
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}
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return Err;
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}
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core_complex::core_complex(sc_core::sc_module_name name)
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: sc_core::sc_module(name)
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, NAMED(initiator)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMED(global_irq_i)
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, NAMED(timer_irq_i)
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, NAMED(local_irq_i, 16)
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, NAMED(elf_file, "")
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, NAMED(enable_disass, false)
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, NAMED(reset_address, 0ULL)
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, NAMED(gdb_server_port, 0)
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, NAMED(dump_ir, false)
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext())
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, tgt_adapter(nullptr)
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#ifdef WITH_SCV
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, m_db(scv_tr_db::get_default_db())
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, stream_handle(nullptr)
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, instr_tr_handle(nullptr)
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, fetch_tr_handle(nullptr)
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#endif
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{
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initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = read_lut.getEntry(start);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
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read_lut.removeEntry(lut_entry);
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}
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lut_entry = write_lut.getEntry(start);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
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write_lut.removeEntry(lut_entry);
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}
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});
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SC_THREAD(run);
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SC_METHOD(clk_cb);
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sensitive << clk_i;
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SC_METHOD(rst_cb);
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sensitive << rst_i;
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SC_METHOD(sw_irq_cb);
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sensitive<<sw_irq_i;
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SC_METHOD(timer_irq_cb);
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sensitive<<timer_irq_i;
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SC_METHOD(global_irq_cb);
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sensitive<<global_irq_i;
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}
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core_complex::~core_complex() = default;
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void core_complex::trace(sc_core::sc_trace_file *trf) {}
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void core_complex::before_end_of_elaboration() {
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cpu = make_unique<core_wrapper>(this);
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vm = create<arch::rv32imac>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
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#ifdef WITH_SCV
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vm->setDisassEnabled(enable_disass.get_value() || m_db!=nullptr);
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#else
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vm->setDisassEnabled(enable_disass.get_value());
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#endif
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auto* srv = debugger::server<debugger::gdb_session>::get();
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if(srv) tgt_adapter = srv->get_target();
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if(tgt_adapter)
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tgt_adapter->add_custom_command({
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"sysc",
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[this](int argc, char* argv[], debugger::out_func of, debugger::data_func df)-> int {
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return cmd_sysc(argc, argv, of, df, tgt_adapter);
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},
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"SystemC sub-commands: break <time>, print_time"});
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}
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void core_complex::start_of_simulation() {
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quantum_keeper.reset();
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if (elf_file.get_value().size() > 0){
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std::pair<uint64_t,bool> start_addr=cpu->load_file(elf_file.get_value());
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if(reset_address.is_default_value() && start_addr.second==true) reset_address.set_value(start_addr.first);
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}
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#ifdef WITH_SCV
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if (m_db!=nullptr && stream_handle == nullptr) {
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string basename(this->name());
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stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
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instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
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fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
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}
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#endif
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}
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void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
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#ifdef WITH_SCV
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if (m_db==nullptr) return;
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if(tr_handle.is_active()) tr_handle.end_transaction();
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tr_handle = instr_tr_handle->begin_transaction();
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tr_handle.record_attribute("PC", pc);
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tr_handle.record_attribute("INSTR", instr_str);
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tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
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tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
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tr_handle.record_attribute("LTIME_START", quantum_keeper.get_current_time().value()/1000);
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#endif
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}
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void core_complex::clk_cb() {
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curr_clk = clk_i.read();
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if(curr_clk==SC_ZERO_TIME) cpu->set_interrupt_execution(true);
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}
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void core_complex::rst_cb() {
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if(rst_i.read())
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cpu->set_interrupt_execution(true);
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}
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void core_complex::sw_irq_cb(){
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if(sw_irq_i.read()) cpu->local_irq(16);
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}
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void core_complex::timer_irq_cb(){
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if(timer_irq_i.read()) cpu->local_irq(17);
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}
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void core_complex::global_irq_cb(){
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if(timer_irq_i.read()) cpu->local_irq(18);
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}
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void core_complex::run() {
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wait(SC_ZERO_TIME); // separate from elaboration phase
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do{
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if(rst_i.read()){
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cpu->reset(reset_address.get_value());
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wait(rst_i.negedge_event());
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}
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while(clk_i.read()==SC_ZERO_TIME){
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wait(clk_i.value_changed_event());
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}
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cpu->set_interrupt_execution(false);
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vm->start();
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} while(cpu->get_interrupt_execution());
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sc_stop();
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}
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bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
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auto lut_entry = read_lut.getEntry(addr);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
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addr + length <= lut_entry.get_end_address() + 1) {
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auto offset = addr - lut_entry.get_start_address();
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std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
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quantum_keeper.inc(lut_entry.get_read_latency());
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return true;
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} else {
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tlm::tlm_generic_payload gp;
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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gp.set_data_ptr(data);
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gp.set_data_length(length);
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gp.set_streaming_width(length);
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auto delay{quantum_keeper.get_local_time()};
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#ifdef WITH_SCV
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if(m_db!=nullptr && tr_handle.is_valid()){
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if(is_fetch && tr_handle.is_active()){
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tr_handle.end_transaction();
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}
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auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
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gp.set_extension(preExt);
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}
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#endif
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initiator->b_transport(gp, delay);
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LOG(TRACE) << "read_mem(0x" << std::hex << addr << ") : " << data;
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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return false;
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}
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if (gp.is_dmi_allowed()) {
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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tlm_dmi_ext dmi_data;
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if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
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if (dmi_data.is_read_allowed())
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read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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if (dmi_data.is_write_allowed())
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write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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}
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}
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return true;
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}
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}
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bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *const data) {
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auto lut_entry = write_lut.getEntry(addr);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
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addr + length <= lut_entry.get_end_address() + 1) {
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auto offset = addr - lut_entry.get_start_address();
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std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
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quantum_keeper.inc(lut_entry.get_read_latency());
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return true;
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} else {
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write_buf.resize(length);
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std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
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tlm::tlm_generic_payload gp;
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_address(addr);
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gp.set_data_ptr(write_buf.data());
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gp.set_data_length(length);
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gp.set_streaming_width(length);
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auto delay{quantum_keeper.get_local_time()};
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#ifdef WITH_SCV
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if(m_db!=nullptr && tr_handle.is_valid()){
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auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
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gp.set_extension(preExt);
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}
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#endif
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initiator->b_transport(gp, delay);
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quantum_keeper.set(delay);
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LOG(TRACE) << "write_mem(0x" << std::hex << addr << ") : " << data;
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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return false;
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}
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if (gp.is_dmi_allowed()) {
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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tlm_dmi_ext dmi_data;
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if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
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if (dmi_data.is_read_allowed())
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read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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if (dmi_data.is_write_allowed())
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write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
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dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
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}
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}
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return true;
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}
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}
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bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
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auto lut_entry = read_lut.getEntry(addr);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
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addr + length <= lut_entry.get_end_address() + 1) {
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auto offset = addr - lut_entry.get_start_address();
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std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
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quantum_keeper.inc(lut_entry.get_read_latency());
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return true;
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} else {
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tlm::tlm_generic_payload gp;
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(addr);
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gp.set_data_ptr(data);
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gp.set_data_length(length);
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gp.set_streaming_width(length);
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return initiator->transport_dbg(gp) == length;
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|
}
|
|
}
|
|
|
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bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
|
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auto lut_entry = write_lut.getEntry(addr);
|
|
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
|
|
addr + length <= lut_entry.get_end_address() + 1) {
|
|
auto offset = addr - lut_entry.get_start_address();
|
|
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
|
|
quantum_keeper.inc(lut_entry.get_read_latency());
|
|
return true;
|
|
} else {
|
|
write_buf.resize(length);
|
|
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
|
|
tlm::tlm_generic_payload gp;
|
|
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
|
gp.set_address(addr);
|
|
gp.set_data_ptr(write_buf.data());
|
|
gp.set_data_length(length);
|
|
gp.set_streaming_width(length);
|
|
return initiator->transport_dbg(gp) == length;
|
|
}
|
|
}
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|
|
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} /* namespace SiFive */
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} /* namespace sysc */
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