175 lines
2.6 KiB
Plaintext
175 lines
2.6 KiB
Plaintext
regfile spi_regs {
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lsb0;
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reg {
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name="sckdiv";
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desc="Serial clock divisor";
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field {
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name ="div";
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} div[12];
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} sckdiv @0x000;
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reg {
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name="sckmode";
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desc="Serial clock mode";
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field {
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name="pha";
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} pha[1];
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field {
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name="pol";
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} pol[1];
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} sckmode @0x004;
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reg {
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name="csid";
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desc="Chip select ID";
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field {
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name="csid";
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} csid[32];
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} csid @0x010;
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reg {
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name="csdef";
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desc="Chip select default";
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field {
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name="csdef";
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} csdef[32];
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} csdef @0x014;
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reg {
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name="csmode";
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desc="Chip select mode";
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field {
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name="mode";
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} mode[2];
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} csmode @0x018;
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reg {
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name="delay0";
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desc="Delay control 0";
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field {
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name="cssck";
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} cssck[7:0];
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field {
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name ="sckcs";
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} sckcs[23:16];
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} delay0 @0x028;
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reg {
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name="delay1";
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desc="Delay control 1";
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field {
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name="intercs";
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}intercs[15:0];
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field {
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name="interxfr";
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} interxfr[23:16];
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} delay1 @0x02C;
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reg {
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name="fmt";
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desc="Frame format";
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field{
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name ="proto";
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}proto[2];
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field {
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name="endian";
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} endian[1];
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field {
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name="dir";
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} dir[1];
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field {
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name="len";
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} len[19:16];
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} fmt @0x040;
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reg {
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name="txdata";
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desc="Tx FIFO data";
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field {
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name="data";
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} data[8];
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field {
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name="full";
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} full[31:31];
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} txdata @0x048;
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reg {
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name="rxdata";
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desc="Rx FIFO data";
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field{
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name="data";
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} data[8];
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field{
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name="empty";
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} empty[31:31];
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} rxdata @0x04C;
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reg {
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name="txmark";
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desc="Tx FIFO watermark";
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field {
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name="txmark";
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} txmark[3];
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} txmark @0x050;
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reg {
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name="rxmark";
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desc="Rx FIFO watermark";
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field {
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name="rxmark";
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} rxmark[3];
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} rxmark @0x054;
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reg {
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name="fctrl";
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desc="SPI flash interface control";
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field {
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name="en";
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} en[1];
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} fctrl @0x060;
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reg {
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name="ffmt";
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desc="SPI flash instruction format";
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field {
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name="cmd_en";
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reset=0x1;
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} cmd_en[1];
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field {
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name="addr_len";
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reset=0x3;
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} addr_len[2];
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field {
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name="pad_cnt";
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reset=0x0;
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} pad_cnt[4];
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field {
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name="cmd_proto";
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reset=0x0;
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} cmd_proto[2];
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field {
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name="addr_proto";
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reset=0x0;
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} addr_proto[2];
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field {
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name="data_proto";
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reset=0x0;
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} data_proto[2];
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field {
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name="cmd_code";
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reset=0x3;
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} cmd_code[23:16];
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field {
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name="pad_code";
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reset=0x0;
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} pad_code[8];
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} ffmt @0x064;
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reg {
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name="ie";
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desc="SPI interrupt enable";
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field{
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name="txwm";
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} txwm[1];
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field{
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name="rxwm";
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} rxwm[1];
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} ie @0x070;
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reg {
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name="ip";
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desc="SPI interrupt pending";
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field{
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name="txwm";
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} txwm[1];
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field{
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name="rxwm";
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} rxwm[1];
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} ip @0x074;
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};
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