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DBT-RISE-TGC/riscv/gen_input
History
Eyck Jentzsch 20b3665003 Back-ported DVCon turorial changes 2018-11-12 19:36:44 +01:00
..
templates Back-ported DVCon turorial changes 2018-11-12 19:36:44 +01:00
.gitignore Refactored code generation to use custom templates 2018-02-09 18:34:26 +00:00
RV32A.core_desc Adapted descriptions to improved Core DSL and regenerated code 2018-05-01 18:33:55 +02:00
RV32C.core_desc Fixed validation errors in core dsl files. 2018-05-09 12:14:59 +02:00
RV32D.core_desc Fixed validation errors in core dsl files. 2018-05-09 12:14:59 +02:00
RV32F.core_desc Fixed validation errors in core dsl files. 2018-05-09 12:14:59 +02:00
RV32IBase.core_desc Back-ported DVCon turorial changes 2018-11-12 19:36:44 +01:00
RV32M.core_desc Adapted descriptions to improved Core DSL and regenerated code 2018-05-01 18:33:55 +02:00
RV64A.core_desc Adapted descriptions to improved Core DSL and regenerated code 2018-05-01 18:33:55 +02:00
RV64IBase.core_desc Fixed validation errors in core dsl files. 2018-05-09 12:14:59 +02:00
RV64M.core_desc Adapted descriptions to improved Core DSL and regenerated code 2018-05-01 18:33:55 +02:00
minres_rv.core_desc Adapted descriptions to improved Core DSL and regenerated code 2018-05-01 18:33:55 +02:00