Eyck Jentzsch a899d30556 Implemented basic HiFive1-like platform with PLL,tracing etc.		2018-07-13 20:04:07 +02:00
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templates	Implemented basic HiFive1-like platform with PLL,tracing etc.	2018-07-13 20:04:07 +02:00
.gitignore	Refactored code generation to use custom templates	2018-02-09 18:34:26 +00:00
minres_rv.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV32A.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV32C.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32D.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32F.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32IBase.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32M.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV64A.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV64IBase.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV64M.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00