fixes core_complex wrt. tlm quantum and DMI

CMakeLists.txt

@@ -173,7 +173,7 @@ if(SystemC_FOUND)
         string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
         target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
     endforeach()
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
     if(WITH_LLVM)
         target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
     endif()

contrib/.gitignore

@@ -0,0 +1,3 @@
+/results
+/cwr
+/*.xml

contrib/README.md

@@ -1,19 +1,43 @@
- # requires conan version 1.59
- # requires decent cmake version 3.23 for instance
- git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
- cd TGC-ISS/
- setenv COWAREHOME /scratch/rocco/workarea/tools/synopsys/T-2022.06-3
- setenv SNPSLMD_LICENSE_FILE 27001@lic02.arteris.com:5285@lic-node0:5285@lic03:5285@lic-node1
- source $COWAREHOME/SLS/linux/setup.csh pae
- setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
- setenv PATH $COWAREHOME/common/bin/:${PATH}
- setenv LD_LIBRARY_PATH /scratch/rocco/workarea/tools/gcc-9.3.0-install/lib64/
- setenv CC /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//gcc
- setenv CXX /scratch/rocco/workarea/tools/synopsys/T-2022.06-3/SLS/linux/common/bin//g++
- cmake -S . -B build/Debug-PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=/scratch/rocco/partners/minres/TGC-ISS/install
- cd build/Debug-PA/
- make -j 16 install
- cd ../../dbt-rise-tgc/contrib
- setenv TGFS_INSTALL_ROOT /scratch/rocco/partners/minres/TGC-ISS/install/
- # import the TGC core itself
- pct tgc_import.tcl
+# Notes
+
+* requires conan version 1.59
+* requires decent cmake version 3.23
+
+Setup for tcsh:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+setenv TGFS_INSTALL_ROOT `pwd`/install
+setenv COWAREHOME <your SNPS PA installation>
+setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
+source $COWAREHOME/SLS/linux/setup.csh pae
+setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
+setenv PATH $COWAREHOME/common/bin/:${PATH}
+setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
+setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```
+
+Setup for bash:
+
+```
+git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
+cd TGC-ISS/
+export TGFS_INSTALL_ROOT `pwd`/install
+module load tools/pa/T-2022.06
+export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
+export CC=$COWAREHOME/SLS/linux/common/bin/gcc
+export CXX=$COWAREHOME/SLS/linux/common/bin/g++
+cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
+    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
+cmake --build build/PA --target install -j16
+cd dbt-rise-tgc/contrib
+# import the TGC core itself
+pct tgc_import_tb.tcl
+```

contrib/build.tcl

@@ -16,7 +16,7 @@ namespace eval Specification {
                 set libdir "${install_dir}/lib64"
                 set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                 # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
             }
             default {
                puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"

contrib/tgc_import.tcl

@@ -9,8 +9,8 @@ proc getScriptDirectory {} {
     set hardware /HARDWARE/HW/HW
 
 set scriptDir [getScriptDirectory]
-#set top_design_name sysc::tgfs::core_complex
 set top_design_name core_complex
+set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -25,7 +25,8 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::load_modules --set-category modules tgc_import.cc
+::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
 
 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -39,10 +40,11 @@ foreach reset ${resets} {
 
 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}() 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
 ::pct::set_bounds i_${top_design_name} 200 300 100 400
+::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/tgc_import_tb.tcl

@@ -4,7 +4,12 @@ set FW_name ${scriptDir}/hello.elf
 
 puts "instantiate testbench elements"
 ::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
+#::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
 ::pct::set_bounds i_Memory_Generic 1000 300 100 100
+
 ::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
 ::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
 						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
@@ -27,23 +32,25 @@ set reset "Rst"
  ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
  ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
  ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
-# ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
 ::pct::set_bounds ${reset}_reset 300 100 100 100
 
 puts "connecting reset/clock"
 ::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
 ::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
 ::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
 ::pct::add_ports_to_connection C_rst i_Bus/Rst
 
 puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
-::pct::set_param_value $hardware/i_core_complex {Scml Properties} elf_file ${FW_name}
-::pct::set_address i_core_complex/initiator:i_Memory_Generic/MEM 0x0
+::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
+::pct::set_address $hardware/i_${top_design_name}/initiator:i_Memory_Generic/MEM 0x0
+::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
 
-#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
-#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
-#::pct::create_simulation_build_config Debug
-#::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+::pct::create_simulation_build_config Debug
+::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
 # add build settings and save design for next steps
 #::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
 #::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/

src/sysc/core_complex.cpp

@@ -431,7 +431,7 @@ void core_complex::before_end_of_elaboration() {
 }
 
 void core_complex::start_of_simulation() {
-    quantum_keeper.reset();
+    // quantum_keeper.reset();
     if (GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
         string s;
@@ -507,6 +507,7 @@ void core_complex::run() {
         while (curr_clk.read() == SC_ZERO_TIME) {
             wait(curr_clk.value_changed_event());
         }
+        quantum_keeper.reset();
         cpu->set_interrupt_execution(false);
         cpu->start();
     } while (cpu->get_interrupt_execution());
@@ -515,8 +516,7 @@ void core_complex::run() {
 
 bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
     auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
         quantum_keeper.inc(lut_entry.get_read_latency());
@@ -537,7 +537,8 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             gp.set_extension(preExt);
         }
         initiator->b_transport(gp, delay);
-        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
+        quantum_keeper.set(delay);
+        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -549,9 +550,6 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
                 if (dmi_data.is_read_allowed())
                     read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
-                if (dmi_data.is_write_allowed())
-                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
@@ -582,7 +580,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         }
         initiator->b_transport(gp, delay);
         quantum_keeper.set(delay);
-        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
+        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -591,9 +589,6 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
             if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
-                if (dmi_data.is_read_allowed())
-                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
-                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
                 if (dmi_data.is_write_allowed())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@@ -604,14 +599,6 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
 }
 
 bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
-    auto lut_entry = read_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     tlm::tlm_generic_payload gp;
     gp.set_command(tlm::TLM_READ_COMMAND);
     gp.set_address(addr);
@@ -619,18 +606,9 @@ bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const d
     gp.set_data_length(length);
     gp.set_streaming_width(length);
     return initiator->transport_dbg(gp) == length;
-    }
 }
 
 bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
-    auto lut_entry = write_lut.getEntry(addr);
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-        addr + length <= lut_entry.get_end_address() + 1) {
-        auto offset = addr - lut_entry.get_start_address();
-        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
-        return true;
-    } else {
     write_buf.resize(length);
     std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
     tlm::tlm_generic_payload gp;
@@ -640,7 +618,6 @@ bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *
     gp.set_data_length(length);
     gp.set_streaming_width(length);
     return initiator->transport_dbg(gp) == length;
-    }
 }
 } /* namespace SiFive */
 } /* namespace sysc */