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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:aa70d8a54a262179a53310cf9ad8273c78fd5c6f
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
b493745cd7 ... aa70d8a54a

Author SHA1 Message Date
Eyck Jentzsch
aa70d8a54a fixes CLIC to match clicinfo description in CLIC spec 11.04.2023 2023-05-02 17:22:13 +02:00
2 changed files with 0 additions and 12 deletions
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6
src/iss/arch/riscv_hart_m_p.h
View File

@@ -356,7 +356,6 @@ protected:
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb; std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
uint8_t clic_cfg_reg{0}; uint8_t clic_cfg_reg{0};
uint32_t clic_info_reg{0};
std::array<uint32_t, 32> clic_inttrig_reg; std::array<uint32_t, 32> clic_inttrig_reg;
union clic_int_reg_t { union clic_int_reg_t {
struct{ struct{
@@ -521,7 +520,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
csr_wr_cb[mintthresh] = &this_class::write_intthresh; csr_wr_cb[mintthresh] = &this_class::write_intthresh;
clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0}); clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0});
clic_cfg_reg=0x20; clic_cfg_reg=0x20;
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1; csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
insert_mem_range(cfg.clic_base, 0x5000UL, insert_mem_range(cfg.clic_base, 0x5000UL,
@@ -1178,8 +1176,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
if(addr==cfg.clic_base) { // cliccfg if(addr==cfg.clic_base) { // cliccfg
*data=clic_cfg_reg; *data=clic_cfg_reg;
for(auto i=1; i<length; ++i) *(data+i)=0; for(auto i=1; i<length; ++i) *(data+i)=0;
} else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
read_reg_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4; auto offset = ((addr&0x7fff)-0x40)/4;
read_reg_uint32(addr, clic_inttrig_reg[offset], data, length); read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@@ -1196,8 +1192,6 @@ template<typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) { iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
if(addr==cfg.clic_base) { // cliccfg if(addr==cfg.clic_base) { // cliccfg
clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e); clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
// } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4; auto offset = ((addr&0x7fff)-0x40)/4;
write_reg_uint32(addr, clic_inttrig_reg[offset], data, length); write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);

6
src/iss/arch/riscv_hart_mu_p.h
View File

@@ -380,7 +380,6 @@ protected:
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb; std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
uint8_t clic_cfg_reg{0}; uint8_t clic_cfg_reg{0};
uint32_t clic_info_reg{0};
std::array<uint32_t, 32> clic_inttrig_reg; std::array<uint32_t, 32> clic_inttrig_reg;
union clic_int_reg_t { union clic_int_reg_t {
struct{ struct{
@@ -589,7 +588,6 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
} }
clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0}); clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0});
clic_cfg_reg=0x30; clic_cfg_reg=0x30;
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1; csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
@@ -1387,8 +1385,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
if(addr==cfg.clic_base) { // cliccfg if(addr==cfg.clic_base) { // cliccfg
*data=clic_cfg_reg; *data=clic_cfg_reg;
for(auto i=1; i<length; ++i) *(data+i)=0; for(auto i=1; i<length; ++i) *(data+i)=0;
} else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
read_reg_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4; auto offset = ((addr&0x7fff)-0x40)/4;
read_reg_uint32(addr, clic_inttrig_reg[offset], data, length); read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@@ -1405,8 +1401,6 @@ template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) { iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
if(addr==cfg.clic_base) { // cliccfg if(addr==cfg.clic_base) { // cliccfg
clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e); clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
// } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
auto offset = ((addr&0x7fff)-0x40)/4; auto offset = ((addr&0x7fff)-0x40)/4;
write_reg_uint32(addr, clic_inttrig_reg[offset], data, length); write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);