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base: DBT-RISE:ac8eab6e255561e071a643360f7552af6ff9a369
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:f4ec21007b666af56fc86f510c2251d0c3a7edf9
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
ac8eab6e25 ... f4ec21007b

Author SHA1 Message Date
Eyck Jentzsch
f4ec21007b fix signedness issues 2021-03-11 16:12:28 +00:00
3 changed files with 10 additions and 10 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 8f72c66a57...d51b3e30f5

2
incl/iss/arch/riscv_hart_m_p.h
View File

@@ -421,7 +421,7 @@ private:
iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
reg_t mhartid_reg{0xF};
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;

16
src/vm/interp/vm_tgf_c.cpp
View File

@@ -587,7 +587,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -620,7 +620,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1084,7 +1084,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0;
if(rd != 0) *(X+rd) = *(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0;
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1258,7 +1258,7 @@ private:
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = ((uint8_t)*(X+rs1)) >> shamt;
if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
}
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 25);
@@ -1296,7 +1296,7 @@ private:
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> shamt;
}
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 26);
@@ -1429,7 +1429,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 30);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1528,7 +1528,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 33);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1561,7 +1561,7 @@ private:
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + 4;
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 34);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);